dt-platdata.c 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149
  1. /*
  2. * DO NOT MODIFY
  3. *
  4. * This file was generated by dtoc from a .dtb (device tree binary) file.
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <dt-structs.h>
  9. static const struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
  10. .reg = {0xff100000, 0x1000},
  11. };
  12. U_BOOT_DEVICE(syscon_at_ff100000) = {
  13. .name = "rockchip_rk3328_grf",
  14. .platdata = &dtv_syscon_at_ff100000,
  15. .platdata_size = sizeof(dtv_syscon_at_ff100000),
  16. };
  17. static const struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
  18. .reg = {0xff440000, 0x1000},
  19. .rockchip_grf = 0x3a,
  20. };
  21. U_BOOT_DEVICE(clock_controller_at_ff440000) = {
  22. .name = "rockchip_rk3328_cru",
  23. .platdata = &dtv_clock_controller_at_ff440000,
  24. .platdata_size = sizeof(dtv_clock_controller_at_ff440000),
  25. };
  26. static const struct dtd_rockchip_rk3328_uart dtv_serial_at_ff130000 = {
  27. .clock_frequency = 0x16e3600,
  28. .clocks = {
  29. {&dtv_clock_controller_at_ff440000, {40}},
  30. {&dtv_clock_controller_at_ff440000, {212}},},
  31. .dma_names = {"tx", "rx"},
  32. .dmas = {0x10, 0x6, 0x10, 0x7},
  33. .interrupts = {0x0, 0x39, 0x4},
  34. .pinctrl_0 = 0x26,
  35. .pinctrl_names = "default",
  36. .reg = {0xff130000, 0x100},
  37. .reg_io_width = 0x4,
  38. .reg_shift = 0x2,
  39. };
  40. U_BOOT_DEVICE(serial_at_ff130000) = {
  41. .name = "rockchip_rk3328_uart",
  42. .platdata = &dtv_serial_at_ff130000,
  43. .platdata_size = sizeof(dtv_serial_at_ff130000),
  44. };
  45. static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = {
  46. .bus_width = 0x4,
  47. .cap_mmc_highspeed = true,
  48. .cap_sd_highspeed = true,
  49. .clocks = {
  50. {&dtv_clock_controller_at_ff440000, {317}},
  51. {&dtv_clock_controller_at_ff440000, {33}},
  52. {&dtv_clock_controller_at_ff440000, {74}},
  53. {&dtv_clock_controller_at_ff440000, {78}},},
  54. .disable_wp = true,
  55. .fifo_depth = 0x100,
  56. .interrupts = {0x0, 0xc, 0x4},
  57. .max_frequency = 0x8f0d180,
  58. .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
  59. .pinctrl_names = "default",
  60. .reg = {0xff500000, 0x4000},
  61. .u_boot_spl_fifo_mode = true,
  62. .vmmc_supply = 0x4b,
  63. .vqmmc_supply = 0x1e,
  64. };
  65. U_BOOT_DEVICE(mmc_at_ff500000) = {
  66. .name = "rockchip_rk3328_dw_mshc",
  67. .platdata = &dtv_mmc_at_ff500000,
  68. .platdata_size = sizeof(dtv_mmc_at_ff500000),
  69. };
  70. static const struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = {
  71. .ranges = true,
  72. .rockchip_grf = 0x3a,
  73. };
  74. U_BOOT_DEVICE(pinctrl) = {
  75. .name = "rockchip_rk3328_pinctrl",
  76. .platdata = &dtv_pinctrl,
  77. .platdata_size = sizeof(dtv_pinctrl),
  78. };
  79. static const struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = {
  80. .clocks = {
  81. {&dtv_clock_controller_at_ff440000, {200}},},
  82. .gpio_controller = true,
  83. .interrupt_controller = true,
  84. .interrupts = {0x0, 0x33, 0x4},
  85. .reg = {0xff210000, 0x100},
  86. };
  87. U_BOOT_DEVICE(gpio0_at_ff210000) = {
  88. .name = "rockchip_gpio_bank",
  89. .platdata = &dtv_gpio0_at_ff210000,
  90. .platdata_size = sizeof(dtv_gpio0_at_ff210000),
  91. };
  92. static const struct dtd_regulator_fixed dtv_sdmmc_regulator = {
  93. .gpio = {0x60, 0x1e, 0x1},
  94. .pinctrl_0 = 0x61,
  95. .pinctrl_names = "default",
  96. .regulator_max_microvolt = 0x325aa0,
  97. .regulator_min_microvolt = 0x325aa0,
  98. .regulator_name = "vcc_sd",
  99. .vin_supply = 0x1c,
  100. };
  101. U_BOOT_DEVICE(sdmmc_regulator) = {
  102. .name = "regulator_fixed",
  103. .platdata = &dtv_sdmmc_regulator,
  104. .platdata_size = sizeof(dtv_sdmmc_regulator),
  105. };
  106. static const struct dtd_rockchip_rk3328_dmc dtv_dmc = {
  107. .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
  108. 0xff720000, 0x1000, 0xff798000, 0x1000},
  109. .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
  110. 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
  111. 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
  112. 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
  113. 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
  114. 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
  115. 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
  116. 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
  117. 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
  118. 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
  119. 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
  120. 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
  121. 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
  122. 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
  123. 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
  124. 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
  125. 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
  126. 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
  127. 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
  128. 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
  129. 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
  130. 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
  131. 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
  132. 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
  133. 0x77, 0x77, 0x79, 0x9},
  134. };
  135. U_BOOT_DEVICE(dmc) = {
  136. .name = "rockchip_rk3328_dmc",
  137. .platdata = &dtv_dmc,
  138. .platdata_size = sizeof(dtv_dmc),
  139. };