1
0

630-MIPS-ath79-fix-chained-irq-disable.patch 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102
  1. --- a/arch/mips/ath79/irq.c
  2. +++ b/arch/mips/ath79/irq.c
  3. @@ -26,6 +26,9 @@
  4. #include "common.h"
  5. #include "machtypes.h"
  6. +static struct irq_chip ip2_chip;
  7. +static struct irq_chip ip3_chip;
  8. +
  9. static void ath79_misc_irq_handler(struct irq_desc *desc)
  10. {
  11. void __iomem *base = ath79_reset_base;
  12. @@ -145,8 +148,7 @@ static void ar934x_ip2_irq_init(void)
  13. for (i = ATH79_IP2_IRQ_BASE;
  14. i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  15. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  16. - handle_level_irq);
  17. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  18. irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
  19. }
  20. @@ -174,7 +176,7 @@ static void qca953x_irq_init(void)
  21. for (i = ATH79_IP2_IRQ_BASE;
  22. i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  23. - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
  24. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  25. irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
  26. }
  27. @@ -238,15 +240,13 @@ static void qca955x_irq_init(void)
  28. for (i = ATH79_IP2_IRQ_BASE;
  29. i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  30. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  31. - handle_level_irq);
  32. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  33. irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
  34. for (i = ATH79_IP3_IRQ_BASE;
  35. i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
  36. - irq_set_chip_and_handler(i, &dummy_irq_chip,
  37. - handle_level_irq);
  38. + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
  39. irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
  40. }
  41. @@ -331,13 +331,13 @@ static void qca956x_irq_init(void)
  42. for (i = ATH79_IP2_IRQ_BASE;
  43. i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  44. - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
  45. + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  46. irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
  47. for (i = ATH79_IP3_IRQ_BASE;
  48. i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
  49. - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
  50. + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
  51. irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
  52. @@ -463,8 +463,36 @@ IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar71
  53. #endif
  54. +static void ath79_ip2_disable(struct irq_data *data)
  55. +{
  56. + disable_irq(ATH79_CPU_IRQ(2));
  57. +}
  58. +
  59. +static void ath79_ip2_enable(struct irq_data *data)
  60. +{
  61. + enable_irq(ATH79_CPU_IRQ(2));
  62. +}
  63. +
  64. +static void ath79_ip3_disable(struct irq_data *data)
  65. +{
  66. + disable_irq(ATH79_CPU_IRQ(3));
  67. +}
  68. +
  69. +static void ath79_ip3_enable(struct irq_data *data)
  70. +{
  71. + enable_irq(ATH79_CPU_IRQ(3));
  72. +}
  73. +
  74. void __init arch_init_irq(void)
  75. {
  76. + ip2_chip = dummy_irq_chip;
  77. + ip2_chip.irq_disable = ath79_ip2_disable;
  78. + ip2_chip.irq_enable = ath79_ip2_enable;
  79. +
  80. + ip3_chip = dummy_irq_chip;
  81. + ip3_chip.irq_disable = ath79_ip3_disable;
  82. + ip3_chip.irq_enable = ath79_ip3_enable;
  83. +
  84. if (mips_machtype == ATH79_MACH_GENERIC_OF) {
  85. irqchip_init();
  86. return;