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601-MIPS-ath79-add-more-register-defines.patch 16 KB

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  1. --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  2. +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  3. @@ -20,6 +20,10 @@
  4. #include <linux/bitops.h>
  5. #define AR71XX_APB_BASE 0x18000000
  6. +#define AR71XX_GE0_BASE 0x19000000
  7. +#define AR71XX_GE0_SIZE 0x10000
  8. +#define AR71XX_GE1_BASE 0x1a000000
  9. +#define AR71XX_GE1_SIZE 0x10000
  10. #define AR71XX_EHCI_BASE 0x1b000000
  11. #define AR71XX_EHCI_SIZE 0x1000
  12. #define AR71XX_OHCI_BASE 0x1c000000
  13. @@ -39,6 +43,8 @@
  14. #define AR71XX_PLL_SIZE 0x100
  15. #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
  16. #define AR71XX_RESET_SIZE 0x100
  17. +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
  18. +#define AR71XX_MII_SIZE 0x100
  19. #define AR71XX_PCI_MEM_BASE 0x10000000
  20. #define AR71XX_PCI_MEM_SIZE 0x07000000
  21. @@ -81,15 +87,21 @@
  22. #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
  23. #define AR933X_UART_SIZE 0x14
  24. +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
  25. +#define AR933X_GMAC_SIZE 0x04
  26. #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
  27. #define AR933X_WMAC_SIZE 0x20000
  28. #define AR933X_EHCI_BASE 0x1b000000
  29. #define AR933X_EHCI_SIZE 0x1000
  30. +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
  31. +#define AR934X_GMAC_SIZE 0x14
  32. #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
  33. #define AR934X_WMAC_SIZE 0x20000
  34. #define AR934X_EHCI_BASE 0x1b000000
  35. #define AR934X_EHCI_SIZE 0x200
  36. +#define AR934X_NFC_BASE 0x1b000200
  37. +#define AR934X_NFC_SIZE 0xb8
  38. #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
  39. #define AR934X_SRIF_SIZE 0x1000
  40. @@ -106,11 +118,15 @@
  41. #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
  42. #define QCA955X_PCI_CTRL_SIZE 0x100
  43. +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
  44. +#define QCA955X_GMAC_SIZE 0x40
  45. #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
  46. #define QCA955X_WMAC_SIZE 0x20000
  47. #define QCA955X_EHCI0_BASE 0x1b000000
  48. #define QCA955X_EHCI1_BASE 0x1b400000
  49. #define QCA955X_EHCI_SIZE 0x1000
  50. +#define QCA955X_NFC_BASE 0x1b800200
  51. +#define QCA955X_NFC_SIZE 0xb8
  52. #define AR9300_OTP_BASE 0x14000
  53. #define AR9300_OTP_STATUS 0x15f18
  54. @@ -174,6 +190,9 @@
  55. #define AR71XX_AHB_DIV_SHIFT 20
  56. #define AR71XX_AHB_DIV_MASK 0x7
  57. +#define AR71XX_ETH0_PLL_SHIFT 17
  58. +#define AR71XX_ETH1_PLL_SHIFT 19
  59. +
  60. #define AR724X_PLL_REG_CPU_CONFIG 0x00
  61. #define AR724X_PLL_REG_PCIE_CONFIG 0x18
  62. @@ -186,6 +205,8 @@
  63. #define AR724X_DDR_DIV_SHIFT 22
  64. #define AR724X_DDR_DIV_MASK 0x3
  65. +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
  66. +
  67. #define AR913X_PLL_REG_CPU_CONFIG 0x00
  68. #define AR913X_PLL_REG_ETH_CONFIG 0x04
  69. #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
  70. @@ -198,6 +219,9 @@
  71. #define AR913X_AHB_DIV_SHIFT 19
  72. #define AR913X_AHB_DIV_MASK 0x1
  73. +#define AR913X_ETH0_PLL_SHIFT 20
  74. +#define AR913X_ETH1_PLL_SHIFT 22
  75. +
  76. #define AR933X_PLL_CPU_CONFIG_REG 0x00
  77. #define AR933X_PLL_CLOCK_CTRL_REG 0x08
  78. @@ -219,6 +243,8 @@
  79. #define AR934X_PLL_CPU_CONFIG_REG 0x00
  80. #define AR934X_PLL_DDR_CONFIG_REG 0x04
  81. #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
  82. +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
  83. +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
  84. #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
  85. #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
  86. @@ -251,9 +277,13 @@
  87. #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
  88. #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  89. +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
  90. +
  91. #define QCA955X_PLL_CPU_CONFIG_REG 0x00
  92. #define QCA955X_PLL_DDR_CONFIG_REG 0x04
  93. #define QCA955X_PLL_CLK_CTRL_REG 0x08
  94. +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
  95. +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
  96. #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
  97. #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
  98. @@ -378,16 +408,83 @@
  99. #define AR913X_RESET_USB_HOST BIT(5)
  100. #define AR913X_RESET_USB_PHY BIT(4)
  101. +#define AR933X_RESET_GE1_MDIO BIT(23)
  102. +#define AR933X_RESET_GE0_MDIO BIT(22)
  103. +#define AR933X_RESET_GE1_MAC BIT(13)
  104. #define AR933X_RESET_WMAC BIT(11)
  105. +#define AR933X_RESET_GE0_MAC BIT(9)
  106. #define AR933X_RESET_USB_HOST BIT(5)
  107. #define AR933X_RESET_USB_PHY BIT(4)
  108. #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
  109. +#define AR934X_RESET_HOST BIT(31)
  110. +#define AR934X_RESET_SLIC BIT(30)
  111. +#define AR934X_RESET_HDMA BIT(29)
  112. +#define AR934X_RESET_EXTERNAL BIT(28)
  113. +#define AR934X_RESET_RTC BIT(27)
  114. +#define AR934X_RESET_PCIE_EP_INT BIT(26)
  115. +#define AR934X_RESET_CHKSUM_ACC BIT(25)
  116. +#define AR934X_RESET_FULL_CHIP BIT(24)
  117. +#define AR934X_RESET_GE1_MDIO BIT(23)
  118. +#define AR934X_RESET_GE0_MDIO BIT(22)
  119. +#define AR934X_RESET_CPU_NMI BIT(21)
  120. +#define AR934X_RESET_CPU_COLD BIT(20)
  121. +#define AR934X_RESET_HOST_RESET_INT BIT(19)
  122. +#define AR934X_RESET_PCIE_EP BIT(18)
  123. +#define AR934X_RESET_UART1 BIT(17)
  124. +#define AR934X_RESET_DDR BIT(16)
  125. +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
  126. +#define AR934X_RESET_NANDF BIT(14)
  127. +#define AR934X_RESET_GE1_MAC BIT(13)
  128. +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
  129. #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
  130. +#define AR934X_RESET_HOST_DMA_INT BIT(10)
  131. +#define AR934X_RESET_GE0_MAC BIT(9)
  132. +#define AR934X_RESET_ETH_SWITCH BIT(8)
  133. +#define AR934X_RESET_PCIE_PHY BIT(7)
  134. +#define AR934X_RESET_PCIE BIT(6)
  135. #define AR934X_RESET_USB_HOST BIT(5)
  136. #define AR934X_RESET_USB_PHY BIT(4)
  137. #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
  138. +#define AR934X_RESET_LUT BIT(2)
  139. +#define AR934X_RESET_MBOX BIT(1)
  140. +#define AR934X_RESET_I2S BIT(0)
  141. +
  142. +#define QCA955X_RESET_HOST BIT(31)
  143. +#define QCA955X_RESET_SLIC BIT(30)
  144. +#define QCA955X_RESET_HDMA BIT(29)
  145. +#define QCA955X_RESET_EXTERNAL BIT(28)
  146. +#define QCA955X_RESET_RTC BIT(27)
  147. +#define QCA955X_RESET_PCIE_EP_INT BIT(26)
  148. +#define QCA955X_RESET_CHKSUM_ACC BIT(25)
  149. +#define QCA955X_RESET_FULL_CHIP BIT(24)
  150. +#define QCA955X_RESET_GE1_MDIO BIT(23)
  151. +#define QCA955X_RESET_GE0_MDIO BIT(22)
  152. +#define QCA955X_RESET_CPU_NMI BIT(21)
  153. +#define QCA955X_RESET_CPU_COLD BIT(20)
  154. +#define QCA955X_RESET_HOST_RESET_INT BIT(19)
  155. +#define QCA955X_RESET_PCIE_EP BIT(18)
  156. +#define QCA955X_RESET_UART1 BIT(17)
  157. +#define QCA955X_RESET_DDR BIT(16)
  158. +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
  159. +#define QCA955X_RESET_NANDF BIT(14)
  160. +#define QCA955X_RESET_GE1_MAC BIT(13)
  161. +#define QCA955X_RESET_SGMII_ANALOG BIT(12)
  162. +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
  163. +#define QCA955X_RESET_HOST_DMA_INT BIT(10)
  164. +#define QCA955X_RESET_GE0_MAC BIT(9)
  165. +#define QCA955X_RESET_SGMII BIT(8)
  166. +#define QCA955X_RESET_PCIE_PHY BIT(7)
  167. +#define QCA955X_RESET_PCIE BIT(6)
  168. +#define QCA955X_RESET_USB_HOST BIT(5)
  169. +#define QCA955X_RESET_USB_PHY BIT(4)
  170. +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
  171. +#define QCA955X_RESET_LUT BIT(2)
  172. +#define QCA955X_RESET_MBOX BIT(1)
  173. +#define QCA955X_RESET_I2S BIT(0)
  174. +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
  175. +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
  176. #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
  177. #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
  178. @@ -529,8 +626,22 @@
  179. #define AR71XX_GPIO_REG_INT_ENABLE 0x24
  180. #define AR71XX_GPIO_REG_FUNC 0x28
  181. +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
  182. +#define AR934X_GPIO_REG_OUT_FUNC1 0x30
  183. +#define AR934X_GPIO_REG_OUT_FUNC2 0x34
  184. +#define AR934X_GPIO_REG_OUT_FUNC3 0x38
  185. +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
  186. +#define AR934X_GPIO_REG_OUT_FUNC5 0x40
  187. #define AR934X_GPIO_REG_FUNC 0x6c
  188. +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
  189. +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
  190. +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
  191. +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
  192. +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
  193. +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
  194. +#define QCA955X_GPIO_REG_FUNC 0x6c
  195. +
  196. #define AR71XX_GPIO_COUNT 16
  197. #define AR7240_GPIO_COUNT 18
  198. #define AR7241_GPIO_COUNT 20
  199. @@ -560,4 +671,235 @@
  200. #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
  201. #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  202. +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
  203. +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
  204. +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
  205. +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
  206. +#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
  207. +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
  208. +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
  209. +
  210. +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
  211. +#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
  212. +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
  213. +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
  214. +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
  215. +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
  216. +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
  217. +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
  218. +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
  219. +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
  220. +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
  221. +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
  222. +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
  223. +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
  224. +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
  225. +#define AR724X_GPIO_FUNC_UART_EN BIT(1)
  226. +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
  227. +
  228. +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
  229. +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
  230. +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
  231. +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
  232. +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
  233. +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
  234. +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
  235. +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
  236. +#define AR913X_GPIO_FUNC_UART_EN BIT(8)
  237. +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
  238. +
  239. +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
  240. +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
  241. +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
  242. +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
  243. +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
  244. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
  245. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
  246. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
  247. +#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
  248. +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
  249. +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
  250. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
  251. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
  252. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
  253. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
  254. +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
  255. +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
  256. +#define AR933X_GPIO_FUNC_UART_EN BIT(1)
  257. +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
  258. +
  259. +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
  260. +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
  261. +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
  262. +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
  263. +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
  264. +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
  265. +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
  266. +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
  267. +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
  268. +
  269. +#define AR934X_GPIO_OUT_GPIO 0
  270. +#define AR934X_GPIO_OUT_SPI_CS1 7
  271. +#define AR934X_GPIO_OUT_LED_LINK0 41
  272. +#define AR934X_GPIO_OUT_LED_LINK1 42
  273. +#define AR934X_GPIO_OUT_LED_LINK2 43
  274. +#define AR934X_GPIO_OUT_LED_LINK3 44
  275. +#define AR934X_GPIO_OUT_LED_LINK4 45
  276. +#define AR934X_GPIO_OUT_EXT_LNA0 46
  277. +#define AR934X_GPIO_OUT_EXT_LNA1 47
  278. +
  279. +#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
  280. +#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
  281. +#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
  282. +#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
  283. +#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
  284. +#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
  285. +#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
  286. +#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
  287. +
  288. +#define QCA955X_GPIO_OUT_GPIO 0
  289. +#define QCA955X_MII_EXT_MDI 1
  290. +#define QCA955X_SLIC_DATA_OUT 3
  291. +#define QCA955X_SLIC_PCM_FS 4
  292. +#define QCA955X_SLIC_PCM_CLK 5
  293. +#define QCA955X_SPI_CLK 8
  294. +#define QCA955X_SPI_CS_0 9
  295. +#define QCA955X_SPI_CS_1 10
  296. +#define QCA955X_SPI_CS_2 11
  297. +#define QCA955X_SPI_MISO 12
  298. +#define QCA955X_I2S_CLK 13
  299. +#define QCA955X_I2S_WS 14
  300. +#define QCA955X_I2S_SD 15
  301. +#define QCA955X_I2S_MCK 16
  302. +#define QCA955X_SPDIF_OUT 17
  303. +#define QCA955X_UART1_TD 18
  304. +#define QCA955X_UART1_RTS 19
  305. +#define QCA955X_UART1_RD 20
  306. +#define QCA955X_UART1_CTS 21
  307. +#define QCA955X_UART0_SOUT 22
  308. +#define QCA955X_SPDIF2_OUT 23
  309. +#define QCA955X_LED_SGMII_SPEED0 24
  310. +#define QCA955X_LED_SGMII_SPEED1 25
  311. +#define QCA955X_LED_SGMII_DUPLEX 26
  312. +#define QCA955X_LED_SGMII_LINK_UP 27
  313. +#define QCA955X_SGMII_SPEED0_INVERT 28
  314. +#define QCA955X_SGMII_SPEED1_INVERT 29
  315. +#define QCA955X_SGMII_DUPLEX_INVERT 30
  316. +#define QCA955X_SGMII_LINK_UP_INVERT 31
  317. +#define QCA955X_GE1_MII_MDO 32
  318. +#define QCA955X_GE1_MII_MDC 33
  319. +#define QCA955X_SWCOM2 38
  320. +#define QCA955X_SWCOM3 39
  321. +#define QCA955X_MAC2_GPIO 40
  322. +#define QCA955X_MAC3_GPIO 41
  323. +#define QCA955X_ATT_LED 42
  324. +#define QCA955X_PWR_LED 43
  325. +#define QCA955X_TX_FRAME 44
  326. +#define QCA955X_RX_CLEAR_EXTERNAL 45
  327. +#define QCA955X_LED_NETWORK_EN 46
  328. +#define QCA955X_LED_POWER_EN 47
  329. +#define QCA955X_WMAC_GLUE_WOW 68
  330. +#define QCA955X_RX_CLEAR_EXTENSION 70
  331. +#define QCA955X_CP_NAND_CS1 73
  332. +#define QCA955X_USB_SUSPEND 74
  333. +#define QCA955X_ETH_TX_ERR 75
  334. +#define QCA955X_DDR_DQ_OE 76
  335. +#define QCA955X_CLKREQ_N_EP 77
  336. +#define QCA955X_CLKREQ_N_RC 78
  337. +#define QCA955X_CLK_OBS0 79
  338. +#define QCA955X_CLK_OBS1 80
  339. +#define QCA955X_CLK_OBS2 81
  340. +#define QCA955X_CLK_OBS3 82
  341. +#define QCA955X_CLK_OBS4 83
  342. +#define QCA955X_CLK_OBS5 84
  343. +
  344. +/*
  345. + * MII_CTRL block
  346. + */
  347. +#define AR71XX_MII_REG_MII0_CTRL 0x00
  348. +#define AR71XX_MII_REG_MII1_CTRL 0x04
  349. +
  350. +#define AR71XX_MII_CTRL_IF_MASK 3
  351. +#define AR71XX_MII_CTRL_SPEED_SHIFT 4
  352. +#define AR71XX_MII_CTRL_SPEED_MASK 3
  353. +#define AR71XX_MII_CTRL_SPEED_10 0
  354. +#define AR71XX_MII_CTRL_SPEED_100 1
  355. +#define AR71XX_MII_CTRL_SPEED_1000 2
  356. +
  357. +#define AR71XX_MII0_CTRL_IF_GMII 0
  358. +#define AR71XX_MII0_CTRL_IF_MII 1
  359. +#define AR71XX_MII0_CTRL_IF_RGMII 2
  360. +#define AR71XX_MII0_CTRL_IF_RMII 3
  361. +
  362. +#define AR71XX_MII1_CTRL_IF_RGMII 0
  363. +#define AR71XX_MII1_CTRL_IF_RMII 1
  364. +
  365. +/*
  366. + * AR933X GMAC interface
  367. + */
  368. +#define AR933X_GMAC_REG_ETH_CFG 0x00
  369. +
  370. +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
  371. +#define AR933X_ETH_CFG_MII_GE0 BIT(1)
  372. +#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
  373. +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
  374. +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
  375. +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
  376. +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
  377. +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
  378. +#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
  379. +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
  380. +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
  381. +
  382. +/*
  383. + * AR934X GMAC Interface
  384. + */
  385. +#define AR934X_GMAC_REG_ETH_CFG 0x00
  386. +
  387. +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
  388. +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
  389. +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
  390. +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
  391. +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
  392. +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
  393. +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
  394. +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
  395. +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
  396. +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
  397. +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
  398. +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
  399. +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
  400. +#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
  401. +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
  402. +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
  403. +#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
  404. +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
  405. +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
  406. +
  407. +/*
  408. + * QCA955X GMAC Interface
  409. + */
  410. +
  411. +#define QCA955X_GMAC_REG_ETH_CFG 0x00
  412. +
  413. +#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
  414. +#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
  415. +#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
  416. +#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
  417. +#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
  418. +#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
  419. +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
  420. +#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
  421. +#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
  422. +#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
  423. +#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
  424. +#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
  425. +#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
  426. +#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
  427. +#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
  428. +#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
  429. +#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
  430. +#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
  431. +#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
  432. +
  433. #endif /* __ASM_MACH_AR71XX_REGS_H */