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WL-351.dts 2.0 KB

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  1. /dts-v1/;
  2. #include "rt3050.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. compatible = "WL-351", "ralink,rt3052-soc";
  6. model = "Sitecom WL-351 v1 002";
  7. cfi@1f000000 {
  8. compatible = "cfi-flash";
  9. reg = <0x1f000000 0x800000>;
  10. bank-width = <2>;
  11. device-width = <2>;
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. partition@0 {
  15. label = "u-boot";
  16. reg = <0x0 0x30000>;
  17. read-only;
  18. };
  19. partition@30000 {
  20. label = "u-boot-env";
  21. reg = <0x30000 0x10000>;
  22. read-only;
  23. };
  24. factory: partition@40000 {
  25. label = "factory";
  26. reg = <0x40000 0x10000>;
  27. read-only;
  28. };
  29. partition@50000 {
  30. label = "firmware";
  31. reg = <0x50000 0x3b0000>;
  32. };
  33. };
  34. gpio-leds {
  35. compatible = "gpio-leds";
  36. power {
  37. label = "wl-351:amber:power";
  38. gpios = <&gpio0 8 1>;
  39. };
  40. unpopulated {
  41. label = "wl-351:amber:unpopulated";
  42. gpios = <&gpio0 12 1>;
  43. };
  44. unpopulated2 {
  45. label = "wl-351:blue:unpopulated";
  46. gpios = <&gpio0 13 1>;
  47. };
  48. };
  49. gpio-keys-polled {
  50. compatible = "gpio-keys-polled";
  51. #address-cells = <1>;
  52. #size-cells = <0>;
  53. poll-interval = <20>;
  54. reset {
  55. label = "reset";
  56. gpios = <&gpio0 10 1>;
  57. linux,code = <KEY_RESTART>;
  58. };
  59. wps {
  60. label = "wps";
  61. gpios = <&gpio0 0 1>;
  62. linux,code = <KEY_WPS_BUTTON>;
  63. };
  64. };
  65. rtl8366rb {
  66. compatible = "rtl8366rb";
  67. gpio-sda = <&gpio0 1 0>;
  68. gpio-sck = <&gpio0 2 0>;
  69. };
  70. };
  71. &pinctrl {
  72. state_default: pinctrl0 {
  73. gpio {
  74. ralink,group = "spi", "i2c", "jtag", "mdio", "uartf";
  75. ralink,function = "gpio";
  76. };
  77. rgmii {
  78. ralink,group = "rgmii";
  79. ralink,function = "rgmii";
  80. };
  81. };
  82. };
  83. &ethernet {
  84. mtd-mac-address = <&factory 0x4>;
  85. };
  86. &esw {
  87. ralink,rgmii = <1>;
  88. mediatek,portmap = <0x3f>;
  89. ralink,fct2 = <0x0002500c>;
  90. /*
  91. * ext phy base addr 31, rx/tx clock skew 0,
  92. * turbo mii off, rgmi 3.3v off, port 5 polling off
  93. * port5: enabled, gige, full-duplex, rx/tx-flow-control
  94. * port6: enabled, gige, full-duplex, rx/tx-flow-control
  95. */
  96. ralink,fpa2 = <0x1f003fff>;
  97. };
  98. &wmac {
  99. ralink,mtd-eeprom = <&factory 0>;
  100. };
  101. &otg {
  102. status = "okay";
  103. };