XDXRN502J.dts 1.4 KB

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  1. /dts-v1/;
  2. #include "rt3050.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. compatible = "XDXRN502J", "ralink,rt3052-soc";
  6. model = "XDX RN502J";
  7. cfi@1f000000 {
  8. compatible = "cfi-flash";
  9. reg = <0x1f000000 0x800000>;
  10. bank-width = <2>;
  11. device-width = <2>;
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. partition@0 {
  15. label = "u-boot";
  16. reg = <0x0 0x30000>;
  17. read-only;
  18. };
  19. partition@30000 {
  20. label = "u-boot-env";
  21. reg = <0x30000 0x10000>;
  22. read-only;
  23. };
  24. factory: partition@40000 {
  25. label = "factory";
  26. reg = <0x40000 0x10000>;
  27. read-only;
  28. };
  29. partition@50000 {
  30. label = "firmware";
  31. reg = <0x50000 0x3b0000>;
  32. };
  33. };
  34. gpio-leds {
  35. compatible = "gpio-leds";
  36. wifi {
  37. label = "xdxrn502j:green:wifi";
  38. gpios = <&gpio0 7 1>;
  39. };
  40. power {
  41. label = "xdxrn502j:green:power";
  42. gpios = <&gpio0 9 1>;
  43. };
  44. };
  45. gpio-keys-polled {
  46. compatible = "gpio-keys-polled";
  47. #address-cells = <1>;
  48. #size-cells = <0>;
  49. poll-interval = <20>;
  50. reset {
  51. label = "reset";
  52. gpios = <&gpio0 10 1>;
  53. linux,code = <KEY_RESTART>;
  54. };
  55. };
  56. };
  57. &pinctrl {
  58. state_default: pinctrl0 {
  59. gpio {
  60. ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf";
  61. ralink,function = "gpio";
  62. };
  63. };
  64. };
  65. &ethernet {
  66. mtd-mac-address = <&factory 0x28>;
  67. };
  68. &esw {
  69. mediatek,portmap = <0x3e>;
  70. };
  71. &wmac {
  72. ralink,mtd-eeprom = <&factory 0>;
  73. };
  74. &otg {
  75. status = "okay";
  76. };