Aarch32 xlat_tables lib: Fix MISRA-2012 defects

This patch fixes violation of Rules 2.1, 7.3, 10.1,
10.4, 12.1, 14.3, 14.4, 17.7, 20.9 reported by
MISRA-2012 scan and adds braces for conditional
statements according to the TF-A coding style.

Change-Id: Ib2463601fb43d955c3d901102b6dceaaad6614f3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

lib/xlat_tables/aarch32/nonlpae_tables.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
- * Copyright (c) 2014-2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2014-2020, Arm Limited. All rights reserved.
  * Copyright (c) 2014, STMicroelectronics International N.V.
  * All rights reserved.
  *
@@ -30,8 +30,8 @@ This module is to be used when LPAE is not supported"
 CASSERT(PLAT_VIRT_ADDR_SPACE_SIZE == (1ULL << 32), invalid_vaddr_space_size);
 CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
 
-#define MMU32B_UNSET_DESC	~0ul
-#define MMU32B_INVALID_DESC	0ul
+#define MMU32B_UNSET_DESC	~0UL
+#define MMU32B_INVALID_DESC	0UL
 
 #define MT_UNKNOWN	~0U
 
@@ -40,38 +40,38 @@ CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
  */
 
 /* Sharable */
-#define MMU32B_TTB_S           (1 << 1)
+#define MMU32B_TTB_S           (1U << 1)
 
 /* Not Outer Sharable */
-#define MMU32B_TTB_NOS         (1 << 5)
+#define MMU32B_TTB_NOS         (1U << 5)
 
 /* Normal memory, Inner Non-cacheable */
-#define MMU32B_TTB_IRGN_NC     0
+#define MMU32B_TTB_IRGN_NC     0U
 
 /* Normal memory, Inner Write-Back Write-Allocate Cacheable */
-#define MMU32B_TTB_IRGN_WBWA   (1 << 6)
+#define MMU32B_TTB_IRGN_WBWA   (1U << 6)
 
 /* Normal memory, Inner Write-Through Cacheable */
-#define MMU32B_TTB_IRGN_WT     1
+#define MMU32B_TTB_IRGN_WT     1U
 
 /* Normal memory, Inner Write-Back no Write-Allocate Cacheable */
-#define MMU32B_TTB_IRGN_WB     (1 | (1 << 6))
+#define MMU32B_TTB_IRGN_WB     (1U | (1U << 6))
 
 /* Normal memory, Outer Write-Back Write-Allocate Cacheable */
-#define MMU32B_TTB_RNG_WBWA    (1 << 3)
+#define MMU32B_TTB_RNG_WBWA    (1U << 3)
 
 #define MMU32B_DEFAULT_ATTRS \
 		(MMU32B_TTB_S | MMU32B_TTB_NOS | \
 		 MMU32B_TTB_IRGN_WBWA | MMU32B_TTB_RNG_WBWA)
 
 /* armv7 memory mapping attributes: section mapping */
-#define SECTION_SECURE			(0 << 19)
-#define SECTION_NOTSECURE		(1 << 19)
-#define SECTION_SHARED			(1 << 16)
-#define SECTION_NOTGLOBAL		(1 << 17)
-#define SECTION_ACCESS_FLAG		(1 << 10)
-#define SECTION_UNPRIV			(1 << 11)
-#define SECTION_RO			(1 << 15)
+#define SECTION_SECURE			(0U << 19)
+#define SECTION_NOTSECURE		(1U << 19)
+#define SECTION_SHARED			(1U << 16)
+#define SECTION_NOTGLOBAL		(1U << 17)
+#define SECTION_ACCESS_FLAG		(1U << 10)
+#define SECTION_UNPRIV			(1U << 11)
+#define SECTION_RO			(1U << 15)
 #define SECTION_TEX(tex)		((((tex) >> 2) << 12) | \
 					((((tex) >> 1) & 0x1) << 3) | \
 					(((tex) & 0x1) << 2))
@@ -80,16 +80,16 @@ CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
 #define SECTION_NORMAL_CACHED		\
 				SECTION_TEX(MMU32B_ATTR_IWBWA_OWBWA_INDEX)
 
-#define SECTION_XN			(1 << 4)
-#define SECTION_PXN			(1 << 0)
-#define SECTION_SECTION			(2 << 0)
+#define SECTION_XN			(1U << 4)
+#define SECTION_PXN			(1U << 0)
+#define SECTION_SECTION			(2U << 0)
 
-#define SECTION_PT_NOTSECURE		(1 << 3)
-#define SECTION_PT_PT			(1 << 0)
+#define SECTION_PT_NOTSECURE		(1U << 3)
+#define SECTION_PT_PT			(1U << 0)
 
-#define SMALL_PAGE_SMALL_PAGE		(1 << 1)
-#define SMALL_PAGE_SHARED		(1 << 10)
-#define SMALL_PAGE_NOTGLOBAL		(1 << 11)
+#define SMALL_PAGE_SMALL_PAGE		(1U << 1)
+#define SMALL_PAGE_SHARED		(1U << 10)
+#define SMALL_PAGE_NOTGLOBAL		(1U << 11)
 #define SMALL_PAGE_TEX(tex)		((((tex) >> 2) << 6) | \
 					((((tex) >> 1) & 0x1) << 3) | \
 					(((tex) & 0x1) << 2))
@@ -99,39 +99,39 @@ CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
 				SMALL_PAGE_TEX(MMU32B_ATTR_DEVICE_INDEX)
 #define SMALL_PAGE_NORMAL_CACHED	\
 				SMALL_PAGE_TEX(MMU32B_ATTR_IWBWA_OWBWA_INDEX)
-#define SMALL_PAGE_ACCESS_FLAG		(1 << 4)
-#define SMALL_PAGE_UNPRIV		(1 << 5)
-#define SMALL_PAGE_RO			(1 << 9)
-#define SMALL_PAGE_XN			(1 << 0)
+#define SMALL_PAGE_ACCESS_FLAG		(1U << 4)
+#define SMALL_PAGE_UNPRIV		(1U << 5)
+#define SMALL_PAGE_RO			(1U << 9)
+#define SMALL_PAGE_XN			(1U << 0)
 
 /* The TEX, C and B bits concatenated */
-#define MMU32B_ATTR_DEVICE_INDEX		0x0
-#define MMU32B_ATTR_IWBWA_OWBWA_INDEX		0x1
+#define MMU32B_ATTR_DEVICE_INDEX	0U
+#define MMU32B_ATTR_IWBWA_OWBWA_INDEX	1U
 
 #define MMU32B_PRRR_IDX(idx, tr, nos)	(((tr) << (2 * (idx))) | \
 					 ((uint32_t)(nos) << ((idx) + 24)))
 #define MMU32B_NMRR_IDX(idx, ir, or)	(((ir) << (2 * (idx))) | \
 					 ((uint32_t)(or) << (2 * (idx) + 16)))
-#define MMU32B_PRRR_DS0			(1 << 16)
-#define MMU32B_PRRR_DS1			(1 << 17)
-#define MMU32B_PRRR_NS0			(1 << 18)
-#define MMU32B_PRRR_NS1			(1 << 19)
+#define MMU32B_PRRR_DS0			(1U << 16)
+#define MMU32B_PRRR_DS1			(1U << 17)
+#define MMU32B_PRRR_NS0			(1U << 18)
+#define MMU32B_PRRR_NS1			(1U << 19)
 
 #define DACR_DOMAIN(num, perm)		((perm) << ((num) * 2))
-#define DACR_DOMAIN_PERM_NO_ACCESS	0x0
-#define DACR_DOMAIN_PERM_CLIENT		0x1
-#define DACR_DOMAIN_PERM_MANAGER	0x3
+#define DACR_DOMAIN_PERM_NO_ACCESS	0U
+#define DACR_DOMAIN_PERM_CLIENT		1U
+#define DACR_DOMAIN_PERM_MANAGER	3U
 
-#define NUM_1MB_IN_4GB		(1U << 12)
-#define NUM_4K_IN_1MB		(1U << 8)
+#define NUM_1MB_IN_4GB		(1UL << 12)
+#define NUM_4K_IN_1MB		(1UL << 8)
 
 #define ONE_MB_SHIFT		20
 
 /* mmu 32b integration */
 #define MMU32B_L1_TABLE_SIZE		(NUM_1MB_IN_4GB * 4)
 #define MMU32B_L2_TABLE_SIZE		(NUM_4K_IN_1MB * 4)
-#define MMU32B_L1_TABLE_ALIGN		(1 << 14)
-#define MMU32B_L2_TABLE_ALIGN		(1 << 10)
+#define MMU32B_L1_TABLE_ALIGN		(1U << 14)
+#define MMU32B_L2_TABLE_ALIGN		(1U << 10)
 
 static unsigned int next_xlat;
 static unsigned long long xlat_max_pa;
@@ -190,8 +190,9 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
 	assert(IS_PAGE_ALIGNED(base_va));
 	assert(IS_PAGE_ALIGNED(size));
 
-	if (size == 0U)
+	if (size == 0U) {
 		return;
+	}
 
 	assert(base_pa < end_pa); /* Check for overflows */
 	assert(base_va < end_va);
@@ -249,8 +250,9 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
 #endif /* ENABLE_ASSERTIONS */
 
 	/* Find correct place in mmap to insert new region */
-	while ((mm->base_va < base_va) && (mm->size != 0U))
+	while ((mm->base_va < base_va) && (mm->size != 0U)) {
 		++mm;
+	}
 
 	/*
 	 * If a section is contained inside another one with the same base
@@ -263,8 +265,9 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
 	 * This is required for mmap_region_attr() to get the attributes of the
 	 * small region correctly.
 	 */
-	while ((mm->base_va == base_va) && (mm->size > size))
+	while ((mm->base_va == base_va) && (mm->size > size)) {
 		++mm;
+	}
 
 	/* Make room for new region by moving other regions up by one place */
 	(void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
@@ -277,10 +280,12 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
 	mm->size = size;
 	mm->attr = attr;
 
-	if (end_pa > xlat_max_pa)
+	if (end_pa > xlat_max_pa) {
 		xlat_max_pa = end_pa;
-	if (end_va > xlat_max_va)
+	}
+	if (end_va > xlat_max_va) {
 		xlat_max_va = end_va;
+	}
 }
 
 /* map all memory as shared/global/domain0/no-usr access */
@@ -290,42 +295,44 @@ static uint32_t mmap_desc(unsigned attr, unsigned int addr_pa,
 	uint32_t desc;
 
 	switch (level) {
-	case 1:
-		assert(!(addr_pa & (MMU32B_L1_TABLE_ALIGN - 1)));
+	case 1U:
+		assert((addr_pa & (MMU32B_L1_TABLE_ALIGN - 1)) == 0U);
 
 		desc = SECTION_SECTION | SECTION_SHARED;
 
-		desc |= attr & MT_NS ? SECTION_NOTSECURE : 0;
+		desc |= (attr & MT_NS) != 0U ? SECTION_NOTSECURE : 0U;
 
 		desc |= SECTION_ACCESS_FLAG;
-		desc |= attr & MT_RW ? 0 : SECTION_RO;
+		desc |= (attr & MT_RW) != 0U ? 0U : SECTION_RO;
 
-		desc |= attr & MT_MEMORY ?
+		desc |= (attr & MT_MEMORY) != 0U ?
 			SECTION_NORMAL_CACHED : SECTION_DEVICE;
 
-		if ((attr & MT_RW) || !(attr & MT_MEMORY))
+		if (((attr & MT_RW) != 0U) || ((attr & MT_MEMORY) == 0U)) {
 			desc |= SECTION_XN;
+		}
 		break;
-	case 2:
-		assert(!(addr_pa & (MMU32B_L2_TABLE_ALIGN - 1)));
+	case 2U:
+		assert((addr_pa & (MMU32B_L2_TABLE_ALIGN - 1)) == 0U);
 
 		desc = SMALL_PAGE_SMALL_PAGE | SMALL_PAGE_SHARED;
 
 		desc |= SMALL_PAGE_ACCESS_FLAG;
-		desc |= attr & MT_RW ? 0 : SMALL_PAGE_RO;
+		desc |= (attr & MT_RW) != 0U ? 0U : SMALL_PAGE_RO;
 
-		desc |= attr & MT_MEMORY ?
+		desc |= (attr & MT_MEMORY) != 0U ?
 			SMALL_PAGE_NORMAL_CACHED : SMALL_PAGE_DEVICE;
 
-		if ((attr & MT_RW) || !(attr & MT_MEMORY))
+		if (((attr & MT_RW) != 0U) || ((attr & MT_MEMORY) == 0U)) {
 			desc |= SMALL_PAGE_XN;
+		}
 		break;
 	default:
 		panic();
 	}
 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
 	/* dump only the non-lpae level 2 tables */
-	if (level == 2) {
+	if (level == 2U) {
 		printf(attr & MT_MEMORY ? "MEM" : "dev");
 		printf(attr & MT_RW ? "-rw" : "-RO");
 		printf(attr & MT_NS ? "-NS" : "-S");
@@ -357,26 +364,31 @@ static unsigned int mmap_region_attr(const mmap_region_t *mm, uintptr_t base_va,
 	 */
 	for ( ; ; ++mm) {
 
-		if (mm->size == 0U)
+		if (mm->size == 0U) {
 			return ret; /* Reached end of list */
+		}
 
-		if (mm->base_va > (base_va + size - 1U))
+		if (mm->base_va > (base_va + size - 1U)) {
 			return ret; /* Next region is after area so end */
+		}
 
-		if ((mm->base_va + mm->size - 1U) < base_va)
+		if ((mm->base_va + mm->size - 1U) < base_va) {
 			continue; /* Next region has already been overtaken */
+		}
 
-		if ((ret == 0U) && (mm->attr == *attr))
+		if ((ret == 0U) && (mm->attr == *attr)) {
 			continue; /* Region doesn't override attribs so skip */
+		}
 
 		if ((mm->base_va > base_va) ||
-			((mm->base_va + mm->size - 1U) < (base_va + size - 1U)))
+			((mm->base_va + mm->size - 1U) <
+					(base_va + size - 1U))) {
 			return MT_UNKNOWN; /* Region doesn't fully cover area */
+		}
 
 		*attr = mm->attr;
 		ret = 0U;
 	}
-	return ret;
 }
 
 static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
@@ -384,16 +396,16 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
 						uint32_t *table,
 						unsigned int level)
 {
-	unsigned int level_size_shift = (level == 1) ?
+	unsigned int level_size_shift = (level == 1U) ?
 					ONE_MB_SHIFT : FOUR_KB_SHIFT;
-	unsigned int level_size = 1 << level_size_shift;
-	unsigned int level_index_mask = (level == 1) ?
+	unsigned int level_size = 1U << level_size_shift;
+	unsigned int level_index_mask = (level == 1U) ?
 					(NUM_1MB_IN_4GB - 1) << ONE_MB_SHIFT :
 					(NUM_4K_IN_1MB - 1) << FOUR_KB_SHIFT;
 
-	assert(level == 1 || level == 2);
+	assert((level == 1U) || (level == 2U));
 
-	VERBOSE("init xlat table at %p (level%1d)\n", (void *)table, level);
+	VERBOSE("init xlat table at %p (level%1u)\n", (void *)table, level);
 
 	do  {
 		uint32_t desc = MMU32B_UNSET_DESC;
@@ -405,15 +417,17 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
 		}
 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
 		/* dump only non-lpae level 2 tables content */
-		if (level == 2)
+		if (level == 2U) {
 			printf("      0x%lx %x " + 6 - 2 * level,
 						base_va, level_size);
+		}
 #endif
 		if (mm->base_va >= base_va + level_size) {
 			/* Next region is after area so nothing to map yet */
 			desc = MMU32B_INVALID_DESC;
-		} else if (mm->base_va <= base_va && mm->base_va + mm->size >=
-				base_va + level_size) {
+		} else if ((mm->base_va <= base_va) &&
+				(mm->base_va + mm->size) >=
+				(base_va + level_size)) {
 			/* Next region covers all of area */
 			unsigned int attr = mm->attr;
 			unsigned int r = mmap_region_attr(mm, base_va,
@@ -436,8 +450,8 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
 			 */
 			if (*table) {
 				assert((*table & 3) == SECTION_PT_PT);
-				assert(!(*table & SECTION_PT_NOTSECURE) ==
-							!(mm->attr & MT_NS));
+				assert(((*table & SECTION_PT_NOTSECURE) == 0U)
+						== ((mm->attr & MT_NS) == 0U));
 
 				xlat_table = (*table) &
 						~(MMU32B_L1_TABLE_ALIGN - 1);
@@ -447,11 +461,11 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
 					next_xlat * MMU32B_L2_TABLE_SIZE;
 				next_xlat++;
 				assert(next_xlat <= MAX_XLAT_TABLES);
-				memset((char *)xlat_table, 0,
+				(void)memset((char *)xlat_table, 0,
 					MMU32B_L2_TABLE_SIZE);
 
 				desc = xlat_table | SECTION_PT_PT;
-				desc |= mm->attr & MT_NS ?
+				desc |= (mm->attr & MT_NS) != 0U ?
 					SECTION_PT_NOTSECURE : 0;
 			}
 			/* Recurse to fill in new table */
@@ -461,12 +475,13 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
 		}
 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
 		/* dump only non-lpae level 2 tables content */
-		if (level == 2)
+		if (level == 2U) {
 			printf("\n");
+		}
 #endif
 		*table++ = desc;
 		base_va += level_size;
-	} while (mm->size && (base_va & level_index_mask));
+	} while ((mm->size != 0U) && ((base_va & level_index_mask) != 0U));
 
 	return mm;
 }
@@ -475,17 +490,16 @@ void init_xlat_tables(void)
 {
 	print_mmap();
 
-	assert(!((unsigned int)mmu_l1_base & (MMU32B_L1_TABLE_ALIGN - 1)));
-	assert(!((unsigned int)mmu_l2_base & (MMU32B_L2_TABLE_ALIGN - 1)));
+	assert(((unsigned int)mmu_l1_base & (MMU32B_L1_TABLE_ALIGN - 1)) == 0U);
+	assert(((unsigned int)mmu_l2_base & (MMU32B_L2_TABLE_ALIGN - 1)) == 0U);
 
-	memset(mmu_l1_base, 0, MMU32B_L1_TABLE_SIZE);
+	(void)memset(mmu_l1_base, 0, MMU32B_L1_TABLE_SIZE);
 
 	init_xlation_table_inner(mmap, 0, (uint32_t *)mmu_l1_base, 1);
 
 	VERBOSE("init xlat - max_va=%p, max_pa=%llx\n",
 			(void *)xlat_max_va, xlat_max_pa);
-	assert(xlat_max_va <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
-	assert(xlat_max_pa <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
+	assert(xlat_max_pa <= (PLAT_VIRT_ADDR_SPACE_SIZE - 1));
 }
 
 /*******************************************************************************
@@ -499,7 +513,7 @@ void enable_mmu_svc_mon(unsigned int flags)
 	unsigned int sctlr;
 
 	assert(IS_IN_SECURE());
-	assert((read_sctlr() & SCTLR_M_BIT) == 0);
+	assert((read_sctlr() & SCTLR_M_BIT) == 0U);
 
 	/* Enable Access flag (simplified access permissions) and TEX remap */
 	write_sctlr(read_sctlr() | SCTLR_AFE_BIT | SCTLR_TRE_BIT);
@@ -522,7 +536,7 @@ void enable_mmu_svc_mon(unsigned int flags)
 
 	/* set MMU base xlat table entry (use only TTBR0) */
 	write_ttbr0((uint32_t)mmu_l1_base | MMU32B_DEFAULT_ATTRS);
-	write_ttbr1(0);
+	write_ttbr1(0U);
 
 	/*
 	 * Ensure all translation table writes have drained
@@ -535,14 +549,15 @@ void enable_mmu_svc_mon(unsigned int flags)
 
 	sctlr = read_sctlr();
 	sctlr |= SCTLR_M_BIT;
-#if ARMV7_SUPPORTS_VIRTUALIZATION
+#ifdef ARMV7_SUPPORTS_VIRTUALIZATION
 	sctlr |= SCTLR_WXN_BIT;
 #endif
 
-	if (flags & DISABLE_DCACHE)
+	if ((flags & DISABLE_DCACHE) != 0U) {
 		sctlr &= ~SCTLR_C_BIT;
-	else
+	} else {
 		sctlr |= SCTLR_C_BIT;
+	}
 
 	write_sctlr(sctlr);