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@@ -1,5 +1,5 @@
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/*
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- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
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+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@@ -46,6 +46,8 @@ CPU_MIDR: /* cpu_ops midr */
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CPU_RESET_FUNC: /* cpu_ops reset_func */
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.space 8
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#endif
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+CPU_EXTRA1_FUNC:
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+ .space 8
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#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
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CPU_PWR_DWN_OPS: /* cpu_ops power down functions */
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.space (8 * CPU_MAX_PWR_DWN_OPS)
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@@ -113,6 +115,10 @@ CPU_OPS_SIZE = .
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* _resetfunc:
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* Reset function for the CPU. If there's no CPU reset function,
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* specify CPU_NO_RESET_FUNC
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+ * _extra1:
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+ * This is a placeholder for future per CPU operations. Currently,
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+ * some CPUs use this entry to set a test function to determine if
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+ * the workaround for CVE-2017-5715 needs to be applied or not.
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* _power_down_ops:
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* Comma-separated list of functions to perform power-down
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* operatios on the CPU. At least one, and up to
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@@ -122,8 +128,8 @@ CPU_OPS_SIZE = .
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* CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
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* used to handle power down at subsequent levels
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*/
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- .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
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- _power_down_ops:vararg
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+ .macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
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+ _extra1:req, _power_down_ops:vararg
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.section cpu_ops, "a"
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.align 3
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.type cpu_ops_\_name, %object
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@@ -131,6 +137,7 @@ CPU_OPS_SIZE = .
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#if defined(IMAGE_AT_EL3)
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.quad \_resetfunc
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#endif
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+ .quad \_extra1
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#ifdef IMAGE_BL31
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1:
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/* Insert list of functions */
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@@ -187,6 +194,18 @@ CPU_OPS_SIZE = .
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#endif
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.endm
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+ .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
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+ _power_down_ops:vararg
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+ declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, \
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+ \_power_down_ops
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+ .endm
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+
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+ .macro declare_cpu_ops_workaround_cve_2017_5715 _name:req, _midr:req, \
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+ _resetfunc:req, _extra1:req, _power_down_ops:vararg
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+ declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
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+ \_extra1, \_power_down_ops
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+ .endm
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+
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#if REPORT_ERRATA
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/*
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* Print status of a CPU errata
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