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@@ -12,27 +12,125 @@
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#include <arch_helpers.h>
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#include <common/feat_detect.h>
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-#define ISOLATE_FIELD(reg, feat) \
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- ((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK))
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-
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-#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \
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-static inline bool is_ ## name ## _supported(void) \
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-{ \
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- if ((guard) == FEAT_STATE_DISABLED) { \
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- return false; \
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- } \
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- if ((guard) == FEAT_STATE_ALWAYS) { \
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- return true; \
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- } \
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- return read_func() >= (idvalue); \
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+#define ISOLATE_FIELD(reg, feat, mask) \
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+ ((unsigned int)(((reg) >> (feat)) & mask))
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+
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+#define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \
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+static inline bool is_ ## name ## _supported(void) \
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+{ \
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+ if ((guard) == FEAT_STATE_DISABLED) { \
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+ return false; \
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+ } \
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+ if ((guard) == FEAT_STATE_ALWAYS) { \
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+ return true; \
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+ } \
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+ return read_func(); \
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}
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-#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \
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-static unsigned int read_ ## name ## _id_field(void) \
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-{ \
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- return ISOLATE_FIELD(read_ ## idreg(), idfield); \
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-} \
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-CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard)
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+#define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
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+static inline bool is_ ## name ## _present(void) \
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+{ \
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+ return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
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+ ? true : false; \
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+}
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+
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+#define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \
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+CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
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+CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard)
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+
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+
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+/* +----------------------------+
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+ * | Features supported |
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+ * +----------------------------+
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+ * | GENTIMER |
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+ * +----------------------------+
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+ * | FEAT_PAN |
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+ * +----------------------------+
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+ * | FEAT_VHE |
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+ * +----------------------------+
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+ * | FEAT_TTCNP |
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+ * +----------------------------+
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+ * | FEAT_UAO |
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+ * +----------------------------+
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+ * | FEAT_PACQARMA3 |
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+ * +----------------------------+
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+ * | FEAT_PAUTH |
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+ * +----------------------------+
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+ * | FEAT_TTST |
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+ * +----------------------------+
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+ * | FEAT_BTI |
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+ * +----------------------------+
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+ * | FEAT_MTE2 |
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+ * +----------------------------+
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+ * | FEAT_SSBS |
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+ * +----------------------------+
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+ * | FEAT_NMI |
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+ * +----------------------------+
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+ * | FEAT_GCS |
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+ * +----------------------------+
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+ * | FEAT_EBEP |
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+ * +----------------------------+
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+ * | FEAT_SEBEP |
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+ * +----------------------------+
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+ * | FEAT_SEL2 |
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+ * +----------------------------+
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+ * | FEAT_TWED |
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+ * +----------------------------+
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+ * | FEAT_FGT |
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+ * +----------------------------+
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+ * | FEAT_EC/ECV2 |
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+ * +----------------------------+
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+ * | FEAT_RNG |
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+ * +----------------------------+
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+ * | FEAT_TCR2 |
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+ * +----------------------------+
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+ * | FEAT_S2POE |
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+ * +----------------------------+
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+ * | FEAT_S1POE |
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+ * +----------------------------+
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+ * | FEAT_S2PIE |
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+ * +----------------------------+
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+ * | FEAT_S1PIE |
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+ * +----------------------------+
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+ * | FEAT_AMU/AMUV1P1 |
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+ * +----------------------------+
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+ * | FEAT_MPAM |
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+ * +----------------------------+
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+ * | FEAT_HCX |
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+ * +----------------------------+
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+ * | FEAT_RNG_TRAP |
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+ * +----------------------------+
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+ * | FEAT_RME |
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+ * +----------------------------+
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+ * | FEAT_SB |
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+ * +----------------------------+
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+ * | FEAT_CSV2/CSV3 |
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+ * +----------------------------+
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+ * | FEAT_SPE |
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+ * +----------------------------+
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+ * | FEAT_SVE |
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+ * +----------------------------+
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+ * | FEAT_RAS |
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+ * +----------------------------+
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+ * | FEAT_DIT |
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+ * +----------------------------+
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+ * | FEAT_SYS_REG_TRACE |
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+ * +----------------------------+
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+ * | FEAT_TRF |
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+ * +----------------------------+
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+ * | FEAT_NV/NV2 |
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+ * +----------------------------+
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+ * | FEAT_BRBE |
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+ * +----------------------------+
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+ * | FEAT_TRBE |
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+ * +----------------------------+
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+ * | FEAT_SME/SME2 |
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+ * +----------------------------+
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+ * | FEAT_PMUV3 |
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+ * +----------------------------+
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+ * | FEAT_MTPMU |
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+ * +----------------------------+
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+ */
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static inline bool is_armv7_gentimer_present(void)
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{
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@@ -40,38 +138,28 @@ static inline bool is_armv7_gentimer_present(void)
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return true;
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}
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+/* FEAT_PAN: Privileged access never */
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CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
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- ENABLE_FEAT_PAN)
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-static inline bool is_feat_pan_present(void)
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-{
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- return read_feat_pan_id_field() != 0U;
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-}
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+ ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN)
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+/* FEAT_VHE: Virtualization Host Extensions */
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CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
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- ENABLE_FEAT_VHE)
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+ ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE)
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-static inline bool is_armv8_2_ttcnp_present(void)
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-{
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- return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
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- ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
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-}
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+/* FEAT_TTCNP: Translation table common not private */
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+CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT,
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+ ID_AA64MMFR2_EL1_CNP_MASK, 1U)
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-static inline bool is_feat_uao_present(void)
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-{
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- return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_UAO_SHIFT) &
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- ID_AA64MMFR2_EL1_UAO_MASK) != 0U;
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-}
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+/* FEAT_UAO: User access override */
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+CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT,
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+ ID_AA64MMFR2_EL1_UAO_MASK, 1U)
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-static inline bool is_feat_pacqarma3_present(void)
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-{
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- uint64_t mask_id_aa64isar2 =
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- (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
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- (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT);
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-
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- /* If any of the fields is not zero, QARMA3 algorithm is present */
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- return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U;
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-}
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+/* If any of the fields is not zero, QARMA3 algorithm is present */
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+CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0,
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+ ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
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+ (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U)
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+/* PAUTH */
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static inline bool is_armv8_3_pauth_present(void)
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{
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uint64_t mask_id_aa64isar1 =
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@@ -88,89 +176,81 @@ static inline bool is_armv8_3_pauth_present(void)
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is_feat_pacqarma3_present());
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}
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-static inline bool is_armv8_4_ttst_present(void)
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-{
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- return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
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- ID_AA64MMFR2_EL1_ST_MASK) == 1U;
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-}
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+/* FEAT_TTST: Small translation tables */
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+CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT,
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+ ID_AA64MMFR2_EL1_ST_MASK, 1U)
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-static inline bool is_armv8_5_bti_present(void)
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-{
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- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) &
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- ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
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-}
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+/* FEAT_BTI: Branch target identification */
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+CREATE_FEATURE_PRESENT(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT,
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+ ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED)
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-static inline unsigned int get_armv8_5_mte_support(void)
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-{
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- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
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- ID_AA64PFR1_EL1_MTE_MASK);
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-}
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-static inline unsigned int is_feat_mte2_present(void)
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-{
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- return get_armv8_5_mte_support() >= MTE_IMPLEMENTED_ELX;
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-}
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-
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-static inline bool is_feat_ssbs_present(void)
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-{
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- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
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- ID_AA64PFR1_EL1_SSBS_MASK) != SSBS_NOT_IMPLEMENTED;
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-}
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+/* FEAT_MTE2: Memory tagging extension */
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+CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
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+ ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2)
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-static inline bool is_feat_nmi_present(void)
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-{
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- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_NMI_SHIFT) &
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- ID_AA64PFR1_EL1_NMI_MASK) == NMI_IMPLEMENTED;
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-}
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+/* FEAT_SSBS: Speculative store bypass safe */
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+CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT,
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+ ID_AA64PFR1_EL1_SSBS_MASK, 1U)
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-static inline bool is_feat_gcs_present(void)
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-{
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- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_GCS_SHIFT) &
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- ID_AA64PFR1_EL1_GCS_MASK) == GCS_IMPLEMENTED;
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-}
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+/* FEAT_NMI: Non-maskable interrupts */
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+CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT,
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+ ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED)
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-static inline bool is_feat_ebep_present(void)
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-{
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- return ((read_id_aa64dfr1_el1() >> ID_AA64DFR1_EBEP_SHIFT) &
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- ID_AA64DFR1_EBEP_MASK) == EBEP_IMPLEMENTED;
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-}
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+/* FEAT_EBEP */
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+CREATE_FEATURE_PRESENT(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT,
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+ ID_AA64DFR1_EBEP_MASK, EBEP_IMPLEMENTED)
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-static inline bool is_feat_sebep_present(void)
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-{
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- return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_SEBEP_SHIFT) &
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- ID_AA64DFR0_SEBEP_MASK) == SEBEP_IMPLEMENTED;
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-}
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+/* FEAT_SEBEP */
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+CREATE_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT,
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+ ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED)
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-CREATE_FEATURE_FUNCS_VER(feat_mte2, get_armv8_5_mte_support, MTE_IMPLEMENTED_ELX,
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- ENABLE_FEAT_MTE2)
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+/* FEAT_SEL2: Secure EL2 */
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CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
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- ENABLE_FEAT_SEL2)
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+ ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2)
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+
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+/* FEAT_TWED: Delayed trapping of WFE */
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CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
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- ENABLE_FEAT_TWED)
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+ ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED)
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+
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+/* FEAT_FGT: Fine-grained traps */
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CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
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- ENABLE_FEAT_FGT)
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+ ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT)
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+
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+/* FEAT_ECV: Enhanced Counter Virtualization */
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CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
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- ENABLE_FEAT_ECV)
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-CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
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- ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
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+ ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV)
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+CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
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+ ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
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+/* FEAT_RNG: Random number generator */
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CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
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- ENABLE_FEAT_RNG)
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+ ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG)
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+
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+/* FEAT_TCR2: Support TCR2_ELx regs */
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CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
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- ENABLE_FEAT_TCR2)
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+ ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2)
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+/* FEAT_S2POE */
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CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
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- ENABLE_FEAT_S2POE)
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+ ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE)
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+
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+/* FEAT_S1POE */
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CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
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- ENABLE_FEAT_S1POE)
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+ ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE)
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+
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static inline bool is_feat_sxpoe_supported(void)
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{
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return is_feat_s1poe_supported() || is_feat_s2poe_supported();
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}
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+/* FEAT_S2PIE */
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CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
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- ENABLE_FEAT_S2PIE)
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+ ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE)
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+
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+/* FEAT_S1PIE */
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CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
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- ENABLE_FEAT_S1PIE)
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+ ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE)
|
|
|
+
|
|
|
static inline bool is_feat_sxpie_supported(void)
|
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|
{
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|
return is_feat_s1pie_supported() || is_feat_s2pie_supported();
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@@ -178,13 +258,15 @@ static inline bool is_feat_sxpie_supported(void)
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/* FEAT_GCS: Guarded Control Stack */
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CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
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- ENABLE_FEAT_GCS)
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+ ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS)
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|
/* FEAT_AMU: Activity Monitors Extension */
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CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
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- ENABLE_FEAT_AMU)
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-CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
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- ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
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+ ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU)
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+
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+/* FEAT_AMUV1P1: AMU Extension v1.1 */
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+CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
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+ ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
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/*
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* Return MPAM version:
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@@ -195,46 +277,32 @@ CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
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* 0x11: v1.1 Armv8.4 or later
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*
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*/
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-static inline unsigned int read_feat_mpam_version(void)
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+static inline bool is_feat_mpam_present(void)
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|
{
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- return (unsigned int)((((read_id_aa64pfr0_el1() >>
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+ unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >>
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ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
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- ((read_id_aa64pfr1_el1() >>
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- ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
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+ ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT)
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+ & ID_AA64PFR1_MPAM_FRAC_MASK));
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+ return ret;
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|
}
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|
-CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
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- ENABLE_FEAT_MPAM)
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+CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM)
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/* FEAT_HCX: Extended Hypervisor Configuration Register */
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CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
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- ENABLE_FEAT_HCX)
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+ ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX)
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|
-static inline bool is_feat_rng_trap_present(void)
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|
-{
|
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|
- return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) &
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|
- ID_AA64PFR1_EL1_RNDR_TRAP_MASK)
|
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|
- == RNG_TRAP_IMPLEMENTED);
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|
-}
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|
+/* FEAT_RNG_TRAP: Trapping support */
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|
+CREATE_FEATURE_PRESENT(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
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+ ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED)
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|
|
|
-static inline unsigned int get_armv9_2_feat_rme_support(void)
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|
|
-{
|
|
|
- /*
|
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|
- * Return the RME version, zero if not supported. This function can be
|
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|
- * used as both an integer value for the RME version or compared to zero
|
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|
- * to detect RME presence.
|
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|
- */
|
|
|
- return (unsigned int)(read_id_aa64pfr0_el1() >>
|
|
|
- ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK;
|
|
|
-}
|
|
|
+/* Return the RME version, zero if not supported. */
|
|
|
+CREATE_FEATURE_FUNCS(feat_rme, id_aa64pfr0_el1, ID_AA64PFR0_FEAT_RME_SHIFT,
|
|
|
+ ID_AA64PFR0_FEAT_RME_MASK, 1U, ENABLE_RME)
|
|
|
|
|
|
-/*********************************************************************************
|
|
|
- * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction)
|
|
|
- ********************************************************************************/
|
|
|
-static inline unsigned int read_feat_sb_id_field(void)
|
|
|
-{
|
|
|
- return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT);
|
|
|
-}
|
|
|
+/* FEAT_SB: Speculation barrier instruction */
|
|
|
+CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT,
|
|
|
+ ID_AA64ISAR1_SB_MASK, 1U)
|
|
|
|
|
|
/*
|
|
|
* FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59]
|
|
@@ -248,109 +316,94 @@ static inline unsigned int read_feat_sb_id_field(void)
|
|
|
* implemented.
|
|
|
* 0b0011 - Feature FEAT_CSV2_3 is implemented.
|
|
|
*/
|
|
|
-static inline unsigned int read_feat_csv2_id_field(void)
|
|
|
-{
|
|
|
- return (unsigned int)(read_id_aa64pfr0_el1() >>
|
|
|
- ID_AA64PFR0_CSV2_SHIFT) & ID_AA64PFR0_CSV2_MASK;
|
|
|
-}
|
|
|
|
|
|
-CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field,
|
|
|
- CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2)
|
|
|
-CREATE_FEATURE_FUNCS_VER(feat_csv2_3, read_feat_csv2_id_field,
|
|
|
- CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3)
|
|
|
+CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
|
|
|
+ ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2)
|
|
|
+CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
|
|
|
+ ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3)
|
|
|
|
|
|
/* FEAT_SPE: Statistical Profiling Extension */
|
|
|
CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
|
|
|
- ENABLE_SPE_FOR_NS)
|
|
|
+ ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS)
|
|
|
|
|
|
/* FEAT_SVE: Scalable Vector Extension */
|
|
|
CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
|
|
|
- ENABLE_SVE_FOR_NS)
|
|
|
+ ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS)
|
|
|
|
|
|
/* FEAT_RAS: Reliability, Accessibility, Serviceability */
|
|
|
-CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1,
|
|
|
- ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS)
|
|
|
+CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT,
|
|
|
+ ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS)
|
|
|
|
|
|
/* FEAT_DIT: Data Independent Timing instructions */
|
|
|
-CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1,
|
|
|
- ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT)
|
|
|
+CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT,
|
|
|
+ ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT)
|
|
|
|
|
|
-CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
|
|
|
- ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS)
|
|
|
+/* FEAT_SYS_REG_TRACE */
|
|
|
+CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, ID_AA64DFR0_TRACEVER_SHIFT,
|
|
|
+ ID_AA64DFR0_TRACEVER_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS)
|
|
|
|
|
|
/* FEAT_TRF: TraceFilter */
|
|
|
CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
|
|
|
- ENABLE_TRF_FOR_NS)
|
|
|
+ ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS)
|
|
|
|
|
|
/* FEAT_NV2: Enhanced Nested Virtualization */
|
|
|
-CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0)
|
|
|
-CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field,
|
|
|
- NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS)
|
|
|
+CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT,
|
|
|
+ ID_AA64MMFR2_EL1_NV_MASK, 1U, 0U)
|
|
|
+CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT,
|
|
|
+ ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS)
|
|
|
|
|
|
/* FEAT_BRBE: Branch Record Buffer Extension */
|
|
|
CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
|
|
|
- ENABLE_BRBE_FOR_NS)
|
|
|
+ ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS)
|
|
|
|
|
|
/* FEAT_TRBE: Trace Buffer Extension */
|
|
|
CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
|
|
|
- ENABLE_TRBE_FOR_NS)
|
|
|
+ ID_AA64DFR0_TRACEBUFFER_MASK, 1U, ENABLE_TRBE_FOR_NS)
|
|
|
+
|
|
|
+/* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */
|
|
|
+CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT,
|
|
|
+ ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U)
|
|
|
|
|
|
-static inline unsigned int read_feat_sme_fa64_id_field(void)
|
|
|
-{
|
|
|
- return ISOLATE_FIELD(read_id_aa64smfr0_el1(),
|
|
|
- ID_AA64SMFR0_EL1_SME_FA64_SHIFT);
|
|
|
-}
|
|
|
/* FEAT_SMEx: Scalar Matrix Extension */
|
|
|
CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
|
|
|
- ENABLE_SME_FOR_NS)
|
|
|
-CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field,
|
|
|
- SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS)
|
|
|
+ ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS)
|
|
|
+
|
|
|
+CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
|
|
|
+ ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS)
|
|
|
|
|
|
/*******************************************************************************
|
|
|
* Function to get hardware granularity support
|
|
|
******************************************************************************/
|
|
|
|
|
|
-static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
|
|
|
-{
|
|
|
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
|
|
|
- ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
|
|
|
-}
|
|
|
-
|
|
|
-static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
|
|
|
+static inline bool is_feat_tgran4K_present(void)
|
|
|
{
|
|
|
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
|
|
|
- ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
|
|
|
+ unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
|
|
|
+ ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK);
|
|
|
+ return (tgranx < 8U);
|
|
|
}
|
|
|
|
|
|
-static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
|
|
|
-{
|
|
|
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
|
|
|
- ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
|
|
|
-}
|
|
|
+CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT,
|
|
|
+ ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED)
|
|
|
|
|
|
-static inline unsigned int read_feat_pmuv3_id_field(void)
|
|
|
+static inline bool is_feat_tgran64K_present(void)
|
|
|
{
|
|
|
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT);
|
|
|
+ unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
|
|
|
+ ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK);
|
|
|
+ return (tgranx < 8U);
|
|
|
}
|
|
|
|
|
|
-static inline unsigned int read_feat_mtpmu_id_field(void)
|
|
|
-{
|
|
|
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT);
|
|
|
-}
|
|
|
+/* FEAT_PMUV3 */
|
|
|
+CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT,
|
|
|
+ ID_AA64DFR0_PMUVER_MASK, 1U)
|
|
|
|
|
|
-static inline bool is_feat_mtpmu_supported(void)
|
|
|
+/* FEAT_MTPMU */
|
|
|
+static inline bool is_feat_mtpmu_present(void)
|
|
|
{
|
|
|
- if (DISABLE_MTPMU == FEAT_STATE_DISABLED) {
|
|
|
- return false;
|
|
|
- }
|
|
|
-
|
|
|
- if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) {
|
|
|
- return true;
|
|
|
- }
|
|
|
-
|
|
|
- unsigned int mtpmu = read_feat_mtpmu_id_field();
|
|
|
-
|
|
|
+ unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
|
|
|
+ ID_AA64DFR0_MTPMU_MASK);
|
|
|
return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED);
|
|
|
}
|
|
|
|
|
|
+CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
|
|
|
+
|
|
|
#endif /* ARCH_FEATURES_H */
|