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@@ -268,25 +268,33 @@
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/* VCO = 1300.0 MHz => P = 650 (CPU) */
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pll1: st,pll@0 {
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- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
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- frac = < 0x800 >;
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+ compatible = "st,stm32mp1-pll";
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+ reg = <0>;
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+ cfg = <2 80 0 0 0 PQR(1,0,0)>;
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+ frac = <0x800>;
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};
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
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pll2: st,pll@1 {
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- cfg = < 2 65 1 0 0 PQR(1,1,1) >;
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- frac = < 0x1400 >;
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+ compatible = "st,stm32mp1-pll";
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+ reg = <1>;
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+ cfg = <2 65 1 0 0 PQR(1,1,1)>;
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+ frac = <0x1400>;
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};
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
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pll3: st,pll@2 {
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- cfg = < 1 33 1 16 36 PQR(1,1,1) >;
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- frac = < 0x1a04 >;
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+ compatible = "st,stm32mp1-pll";
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+ reg = <2>;
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+ cfg = <1 33 1 16 36 PQR(1,1,1)>;
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+ frac = <0x1a04>;
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};
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/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
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pll4: st,pll@3 {
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- cfg = < 3 98 5 7 7 PQR(1,1,1) >;
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+ compatible = "st,stm32mp1-pll";
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+ reg = <3>;
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+ cfg = <3 98 5 7 7 PQR(1,1,1)>;
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};
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};
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