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@@ -349,6 +349,12 @@
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#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1)
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#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2)
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+/* ID_AA64MMFR3_EL1 definitions */
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+#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3
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+
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+#define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0)
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+#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
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+
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/* ID_AA64PFR1_EL1 definitions */
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#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
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#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
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@@ -501,6 +507,7 @@
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#define SCR_GPF_BIT (UL(1) << 48)
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#define SCR_TWEDEL_SHIFT U(30)
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#define SCR_TWEDEL_MASK ULL(0xf)
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+#define SCR_TCR2EN_BIT (UL(1) << 43)
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#define SCR_TRNDR_BIT (UL(1) << 40)
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#define SCR_HXEn_BIT (UL(1) << 38)
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#define SCR_ENTP2_SHIFT U(41)
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@@ -1301,6 +1308,11 @@
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#define HCRX_EL2_EnALS_BIT (UL(1) << 1)
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#define HCRX_EL2_EnAS0_BIT (UL(1) << 0)
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+/*******************************************************************************
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+ * FEAT_TCR2 - Extended Translation Control Register
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+ ******************************************************************************/
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+#define TCR2_EL2 S3_4_C2_C0_3
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+
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/*******************************************************************************
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* Definitions for DynamicIQ Shared Unit registers
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******************************************************************************/
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