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+/*
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+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions are met:
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+ *
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+ * Redistributions of source code must retain the above copyright notice, this
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+ * list of conditions and the following disclaimer.
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+ *
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+ * Redistributions in binary form must reproduce the above copyright notice,
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+ * this list of conditions and the following disclaimer in the documentation
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+ * and/or other materials provided with the distribution.
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+ *
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+ * Neither the name of ARM nor the names of its contributors may be used
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+ * to endorse or promote products derived from this software without specific
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+ * prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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+ * POSSIBILITY OF SUCH DAMAGE.
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+ */
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+
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+#include <arch_helpers.h>
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+#include <assert.h>
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+#include <context.h>
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+#include <context_mgmt.h>
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+#include <debug.h>
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+#include <platform.h>
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+#include <smcc_helpers.h>
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+
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+/*
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+ * Following arrays will be used for context management.
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+ * There are 2 instances, for the Secure and Non-Secure contexts.
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+ */
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+static cpu_context_t bl1_cpu_context[2];
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+static smc_ctx_t bl1_smc_context[2];
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+
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+/* Following contains the next cpu context pointer. */
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+static void *bl1_next_cpu_context_ptr;
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+
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+/* Following contains the next smc context pointer. */
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+static void *bl1_next_smc_context_ptr;
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+
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+/* Following functions are used for SMC context handling */
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+void *smc_get_ctx(int security_state)
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+{
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+ assert(sec_state_is_valid(security_state));
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+ return &bl1_smc_context[security_state];
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+}
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+
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+void smc_set_next_ctx(int security_state)
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+{
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+ assert(sec_state_is_valid(security_state));
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+ bl1_next_smc_context_ptr = &bl1_smc_context[security_state];
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+}
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+
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+void *smc_get_next_ctx(void)
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+{
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+ return bl1_next_smc_context_ptr;
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+}
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+
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+/* Following functions are used for CPU context handling */
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+void *cm_get_context(uint32_t security_state)
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+{
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+ assert(sec_state_is_valid(security_state));
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+ return &bl1_cpu_context[security_state];
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+}
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+
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+void cm_set_next_context(void *cpu_context)
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+{
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+ assert(cpu_context);
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+ bl1_next_cpu_context_ptr = cpu_context;
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+}
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+
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+void *cm_get_next_context(void)
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+{
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+ return bl1_next_cpu_context_ptr;
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+}
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+
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+/*******************************************************************************
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+ * Following function copies GP regs r0-r4, lr and spsr,
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+ * from the CPU context to the SMC context structures.
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+ ******************************************************************************/
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+static void copy_cpu_ctx_to_smc_ctx(const regs_t *cpu_reg_ctx,
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+ smc_ctx_t *next_smc_ctx)
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+{
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+ next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
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+ next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
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+ next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
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+ next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3);
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+ next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
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+ next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
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+}
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+
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+/*******************************************************************************
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+ * Following function flushes the SMC & CPU context pointer and its data.
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+ ******************************************************************************/
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+static void flush_smc_and_cpu_ctx(void)
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+{
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+ flush_dcache_range((uintptr_t)&bl1_next_smc_context_ptr,
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+ sizeof(bl1_next_smc_context_ptr));
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+ flush_dcache_range((uintptr_t)bl1_next_smc_context_ptr,
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+ sizeof(smc_ctx_t));
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+
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+ flush_dcache_range((uintptr_t)&bl1_next_cpu_context_ptr,
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+ sizeof(bl1_next_cpu_context_ptr));
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+ flush_dcache_range((uintptr_t)bl1_next_cpu_context_ptr,
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+ sizeof(cpu_context_t));
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+}
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+
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+/*******************************************************************************
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+ * This function prepares the context for Secure/Normal world images.
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+ * Normal world images are transitioned to HYP(if supported) else SVC.
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+ ******************************************************************************/
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+void bl1_prepare_next_image(unsigned int image_id)
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+{
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+ unsigned int security_state;
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+ image_desc_t *image_desc;
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+ entry_point_info_t *next_bl_ep;
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+
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+ /* Get the image descriptor. */
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+ image_desc = bl1_plat_get_image_desc(image_id);
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+ assert(image_desc);
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+
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+ /* Get the entry point info. */
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+ next_bl_ep = &image_desc->ep_info;
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+
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+ /* Get the image security state. */
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+ security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
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+
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+ /* Prepare the SPSR for the next BL image. */
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+ if (security_state == SECURE) {
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+ next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
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+ SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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+ } else {
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+ /* Use HYP mode if supported else use SVC. */
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+ if (GET_VIRT_EXT(read_id_pfr1()) == MODE32_hyp) {
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+ next_bl_ep->spsr = SPSR_MODE32(MODE32_hyp, SPSR_T_ARM,
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+ SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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+ } else {
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+ next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
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+ SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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+ }
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+ }
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+
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+ /* Allow platform to make change */
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+ bl1_plat_set_ep_info(image_id, next_bl_ep);
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+
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+ /* Prepare the cpu context for the next BL image. */
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+ cm_init_my_context(next_bl_ep);
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+ cm_prepare_el3_exit(security_state);
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+ cm_set_next_context(cm_get_context(security_state));
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+
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+ /* Prepare the smc context for the next BL image. */
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+ smc_set_next_ctx(security_state);
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+ copy_cpu_ctx_to_smc_ctx(get_regs_ctx(cm_get_next_context()),
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+ smc_get_next_ctx());
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+
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+ /*
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+ * Flush the SMC & CPU context and the (next)pointers,
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+ * to access them after caches are disabled.
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+ */
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+ flush_smc_and_cpu_ctx();
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+
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+ /* Indicate that image is in execution state. */
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+ image_desc->state = IMAGE_STATE_EXECUTED;
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+
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+ print_entry_point_info(next_bl_ep);
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+}
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Yatharth Kochar