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+/*
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+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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+ *
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+ * SPDX-License-Identifier: BSD-3-Clause
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+ */
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+
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+#include <gicv3.h>
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+#include <interrupt_props.h>
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+#include <platform.h>
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+#include <platform_def.h>
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+#include <utils.h>
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+#include "versal_private.h"
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+
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+/******************************************************************************
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+ * The following functions are defined as weak to allow a platform to override
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+ * the way the GICv3 driver is initialised and used.
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+ *****************************************************************************/
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+#pragma weak plat_versal_gic_driver_init
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+#pragma weak plat_versal_gic_init
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+#pragma weak plat_versal_gic_cpuif_enable
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+#pragma weak plat_versal_gic_cpuif_disable
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+#pragma weak plat_versal_gic_pcpu_init
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+#pragma weak plat_versal_gic_redistif_on
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+#pragma weak plat_versal_gic_redistif_off
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+
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+/* The GICv3 driver only needs to be initialized in EL3 */
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+static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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+
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+static const interrupt_prop_t versal_interrupt_props[] = {
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+ PLAT_VERSAL_G1S_IRQ_PROPS(INTR_GROUP1S),
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+ PLAT_VERSAL_G0_IRQ_PROPS(INTR_GROUP0)
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+};
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+
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+/*
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+ * We save and restore the GICv3 context on system suspend. Allocate the
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+ * data in the designated EL3 Secure carve-out memory.
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+ */
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+static gicv3_redist_ctx_t rdist_ctx __section("versal_el3_tzc_dram");
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+static gicv3_dist_ctx_t dist_ctx __section("versal_el3_tzc_dram");
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+
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+/*
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+ * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
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+ * to core position.
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+ *
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+ * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
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+ * values read from GICR_TYPER don't have an MT field. To reuse the same
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+ * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
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+ * that read from GICR_TYPER.
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+ *
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+ * Assumptions:
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+ *
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+ * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
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+ * - No CPUs implemented in the system use affinity level 3.
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+ */
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+static unsigned int versal_gicv3_mpidr_hash(u_register_t mpidr)
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+{
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+ mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
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+ return versal_calc_core_pos(mpidr);
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+}
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+
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+static const gicv3_driver_data_t versal_gic_data __unused = {
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+ .gicd_base = PLAT_VERSAL_GICD_BASE,
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+ .gicr_base = PLAT_VERSAL_GICR_BASE,
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+ .interrupt_props = versal_interrupt_props,
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+ .interrupt_props_num = ARRAY_SIZE(versal_interrupt_props),
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+ .rdistif_num = PLATFORM_CORE_COUNT,
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+ .rdistif_base_addrs = rdistif_base_addrs,
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+ .mpidr_to_core_pos = versal_gicv3_mpidr_hash
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+};
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+
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+void __init plat_versal_gic_driver_init(void)
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+{
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+ /*
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+ * The GICv3 driver is initialized in EL3 and does not need
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+ * to be initialized again in SEL1. This is because the S-EL1
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+ * can use GIC system registers to manage interrupts and does
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+ * not need GIC interface base addresses to be configured.
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+ */
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+#if IMAGE_BL31
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+ gicv3_driver_init(&versal_gic_data);
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+#endif
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+}
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+
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+/******************************************************************************
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+ * Versal common helper to initialize the GIC. Only invoked by BL31
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+ *****************************************************************************/
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+void __init plat_versal_gic_init(void)
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+{
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+ gicv3_distif_init();
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+ gicv3_rdistif_init(plat_my_core_pos());
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+ gicv3_cpuif_enable(plat_my_core_pos());
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+}
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+
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+/******************************************************************************
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+ * Versal common helper to enable the GIC CPU interface
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+ *****************************************************************************/
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+void plat_versal_gic_cpuif_enable(void)
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+{
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+ gicv3_cpuif_enable(plat_my_core_pos());
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+}
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+
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+/******************************************************************************
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+ * Versal common helper to disable the GIC CPU interface
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+ *****************************************************************************/
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+void plat_versal_gic_cpuif_disable(void)
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+{
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+ gicv3_cpuif_disable(plat_my_core_pos());
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+}
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+
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+/******************************************************************************
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+ * Versal common helper to initialize the per-cpu redistributor interface in
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+ * GICv3
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+ *****************************************************************************/
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+void plat_versal_gic_pcpu_init(void)
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+{
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+ gicv3_rdistif_init(plat_my_core_pos());
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+}
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+
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+/******************************************************************************
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+ * Versal common helpers to power GIC redistributor interface
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+ *****************************************************************************/
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+void plat_versal_gic_redistif_on(void)
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+{
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+ gicv3_rdistif_on(plat_my_core_pos());
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+}
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+
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+void plat_versal_gic_redistif_off(void)
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+{
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+ gicv3_rdistif_off(plat_my_core_pos());
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+}
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+
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+/******************************************************************************
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+ * Versal common helper to save & restore the GICv3 on resume from system
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+ * suspend
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+ *****************************************************************************/
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+void plat_versal_gic_save(void)
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+{
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+ /*
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+ * If an ITS is available, save its context before
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+ * the Redistributor using:
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+ * gicv3_its_save_disable(gits_base, &its_ctx[i])
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+ * Additionnaly, an implementation-defined sequence may
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+ * be required to save the whole ITS state.
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+ */
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+
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+ /*
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+ * Save the GIC Redistributors and ITS contexts before the
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+ * Distributor context. As we only handle SYSTEM SUSPEND API,
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+ * we only need to save the context of the CPU that is issuing
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+ * the SYSTEM SUSPEND call, i.e. the current CPU.
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+ */
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+ gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
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+
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+ /* Save the GIC Distributor context */
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+ gicv3_distif_save(&dist_ctx);
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+
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+ /*
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+ * From here, all the components of the GIC can be safely powered down
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+ * as long as there is an alternate way to handle wakeup interrupt
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+ * sources.
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+ */
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+}
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+
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+void plat_versal_gic_resume(void)
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+{
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+ /* Restore the GIC Distributor context */
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+ gicv3_distif_init_restore(&dist_ctx);
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+
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+ /*
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+ * Restore the GIC Redistributor and ITS contexts after the
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+ * Distributor context. As we only handle SYSTEM SUSPEND API,
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+ * we only need to restore the context of the CPU that issued
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+ * the SYSTEM SUSPEND call.
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+ */
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+ gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
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+
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+ /*
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+ * If an ITS is available, restore its context after
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+ * the Redistributor using:
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+ * gicv3_its_restore(gits_base, &its_ctx[i])
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+ * An implementation-defined sequence may be required to
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+ * restore the whole ITS state. The ITS must also be
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+ * re-enabled after this sequence has been executed.
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+ */
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+}
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