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@@ -1,5 +1,5 @@
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/*
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- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@@ -15,6 +15,11 @@
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#include <plat/arm/common/fconf_sec_intr_config.h>
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#include <plat/common/platform.h>
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+#if FVP_GICR_REGION_PROTECTION
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+/* To indicate GICR region of the core initialized as Read-Write */
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+static bool fvp_gicr_rw_region_init[PLATFORM_CORE_COUNT] = {false};
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+#endif /* FVP_GICR_REGION_PROTECTION */
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+
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/* The GICv3 driver only needs to be initialized in EL3 */
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static uintptr_t fvp_rdistif_base_addrs[PLATFORM_CORE_COUNT];
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@@ -61,8 +66,39 @@ static gicv3_driver_data_t fvp_gic_data = {
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.mpidr_to_core_pos = fvp_gicv3_mpidr_hash
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};
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+/******************************************************************************
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+ * This function gets called per core to make its redistributor frame rw
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+ *****************************************************************************/
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+static void fvp_gicv3_make_rdistrif_rw(void)
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+{
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+#if FVP_GICR_REGION_PROTECTION
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+ unsigned int core_pos = plat_my_core_pos();
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+
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+ /* Make the redistributor frame RW if it is not done previously */
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+ if (fvp_gicr_rw_region_init[core_pos] != true) {
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+ int ret = xlat_change_mem_attributes(BASE_GICR_BASE +
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+ (core_pos * BASE_GICR_SIZE),
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+ BASE_GICR_SIZE,
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+ MT_EXECUTE_NEVER |
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+ MT_DEVICE | MT_RW |
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+ MT_SECURE);
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+
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+ if (ret != 0) {
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+ ERROR("Failed to make redistributor frame \
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+ read write = %d\n", ret);
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+ panic();
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+ } else {
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+ fvp_gicr_rw_region_init[core_pos] = true;
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+ }
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+ }
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+#else
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+ return;
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+#endif /* FVP_GICR_REGION_PROTECTION */
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+}
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+
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void plat_arm_gic_driver_init(void)
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{
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+ fvp_gicv3_make_rdistrif_rw();
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/*
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* Get GICD and GICR base addressed through FCONF APIs.
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* FCONF is not supported in BL32 for FVP.
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@@ -117,6 +153,8 @@ void plat_arm_gic_pcpu_init(void)
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int result;
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const uint64_t *plat_gicr_frames = fvp_gicr_frames;
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+ fvp_gicv3_make_rdistrif_rw();
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+
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do {
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result = gicv3_rdistif_probe(*plat_gicr_frames);
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