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@@ -1,5 +1,5 @@
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/*
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- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@@ -7,6 +7,7 @@
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#define CPU_MACROS_S
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#include <arch.h>
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+#include <assert_macros.S>
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#include <lib/cpus/errata_report.h>
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#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
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@@ -263,11 +264,22 @@
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mrs \_reg, id_aa64pfr0_el1
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ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH
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/*
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- * If the field equals to 1 then branch targets trained in one
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- * context cannot affect speculative execution in a different context.
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+ * If the field equals 1, branch targets trained in one context cannot
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+ * affect speculative execution in a different context.
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+ *
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+ * If the field equals 2, it means that the system is also aware of
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+ * SCXTNUM_ELx register contexts. We aren't using them in the TF, so we
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+ * expect users of the registers to do the right thing.
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+ *
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+ * Only apply mitigations if the value of this field is 0.
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*/
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- cmp \_reg, #1
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- beq \_label
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+#if ENABLE_ASSERTIONS
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+ cmp \_reg, #3 /* Only values 0 to 2 are expected */
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+ ASM_ASSERT(lo)
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+#endif
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+
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+ cmp \_reg, #0
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+ bne \_label
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.endm
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/*
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