Mark Dykes
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2c878eb6c7
Merge "feat(intel): add build option for boot source" into integration
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1 month ago |
Sieu Mun Tang
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beba20403e
fix(intel): refactor SDMMC driver for Altera products
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1 month ago |
Sieu Mun Tang
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ef8b05f559
feat(intel): add build option for boot source
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1 month ago |
Sieu Mun Tang
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1838a39a44
fix(intel): update all the platforms hand-off data offset value
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1 month ago |
Sieu Mun Tang
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f29765fd33
fix(intel): update preloaded_bl33_base for legacy product
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1 month ago |
Sieu Mun Tang
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b3d2850842
fix(intel): update Agilex5 BL2 init flow and other misc changes
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3 months ago |
Sandrine Bailleux
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9c653440f6
Merge changes Id85b2541,I4d253e2f into integration
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10 months ago |
Sieu Mun Tang
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a72f86ac42
fix(intel): update system counter back to 400MHz
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11 months ago |
Jit Loon Lim
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6cf16b3682
feat(intel): support QSPI ECC Linux for N5X
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1 year ago |
Sandrine Bailleux
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9118bdf401
Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration
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11 months ago |
Jit Loon Lim
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150d2be0d2
fix(intel): fix hardcoded mpu frequency ticks
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1 year ago |
Sieu Mun Tang
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47ca43bcb4
feat(intel): restructure watchdog
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1 year ago |
Jit Loon Lim
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7931d3322d
feat(intel): platform enablement for Agilex5 SoC FPGA
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1 year ago |
Jit Loon Lim
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b653f3caf0
feat(intel): restructure sys mgr for S10/N5X
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1 year ago |
Sieu Mun Tang
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02a9d70c4d
feat(intel): implement timer init divider via CPU frequency for N5X
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2 years ago |
Madhukar Pappireddy
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f0f631fd44
Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration
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2 years ago |
BenjaminLimJL
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f65bdf3a54
feat(intel): implement timer init divider via cpu frequency. (#1)
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2 years ago |
Sieu Mun Tang
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11f4f03043
feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge
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2 years ago |
Sieu Mun Tang
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f571183b06
fix(intel): make FPGA memory configurations platform specific
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2 years ago |
Sieu Mun Tang
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325eb35d24
build(intel): add N5X as a new Intel platform
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2 years ago |