Commit History

Author SHA1 Message Date
  Mark Dykes 2c878eb6c7 Merge "feat(intel): add build option for boot source" into integration 1 month ago
  Sieu Mun Tang beba20403e fix(intel): refactor SDMMC driver for Altera products 1 month ago
  Sieu Mun Tang ef8b05f559 feat(intel): add build option for boot source 1 month ago
  Sieu Mun Tang 1838a39a44 fix(intel): update all the platforms hand-off data offset value 1 month ago
  Sieu Mun Tang f29765fd33 fix(intel): update preloaded_bl33_base for legacy product 1 month ago
  Sieu Mun Tang b3d2850842 fix(intel): update Agilex5 BL2 init flow and other misc changes 3 months ago
  Sandrine Bailleux 9c653440f6 Merge changes Id85b2541,I4d253e2f into integration 10 months ago
  Sieu Mun Tang a72f86ac42 fix(intel): update system counter back to 400MHz 11 months ago
  Jit Loon Lim 6cf16b3682 feat(intel): support QSPI ECC Linux for N5X 1 year ago
  Sandrine Bailleux 9118bdf401 Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration 11 months ago
  Jit Loon Lim 150d2be0d2 fix(intel): fix hardcoded mpu frequency ticks 1 year ago
  Sieu Mun Tang 47ca43bcb4 feat(intel): restructure watchdog 1 year ago
  Jit Loon Lim 7931d3322d feat(intel): platform enablement for Agilex5 SoC FPGA 1 year ago
  Jit Loon Lim b653f3caf0 feat(intel): restructure sys mgr for S10/N5X 1 year ago
  Sieu Mun Tang 02a9d70c4d feat(intel): implement timer init divider via CPU frequency for N5X 2 years ago
  Madhukar Pappireddy f0f631fd44 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration 2 years ago
  BenjaminLimJL f65bdf3a54 feat(intel): implement timer init divider via cpu frequency. (#1) 2 years ago
  Sieu Mun Tang 11f4f03043 feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge 2 years ago
  Sieu Mun Tang f571183b06 fix(intel): make FPGA memory configurations platform specific 2 years ago
  Sieu Mun Tang 325eb35d24 build(intel): add N5X as a new Intel platform 2 years ago