 Sieu Mun Tang
|
d0e400b3c6
fix(intel): revert back to use L4 clock
|
há 11 meses atrás |
 Jit Loon Lim
|
150d2be0d2
fix(intel): fix hardcoded mpu frequency ticks
|
há 1 ano atrás |
|
Jit Loon Lim
|
b653f3caf0
feat(intel): restructure sys mgr for S10/N5X
|
há 1 ano atrás |
|
Sieu Mun Tang
|
02a9d70c4d
feat(intel): implement timer init divider via CPU frequency for N5X
|
há 2 anos atrás |
 Madhukar Pappireddy
|
13ce03aa8a
Merge "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC" into integration
|
há 2 anos atrás |
|
BenjaminLimJL
|
f65bdf3a54
feat(intel): implement timer init divider via cpu frequency. (#1)
|
há 2 anos atrás |
|
Sieu Mun Tang
|
bb0fcc7e01
feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC
|
há 2 anos atrás |
 Hadi Asyrafi
|
328718f254
intel: Refactor common platform code [1/5]
|
há 5 anos atrás |
|
Hadi Asyrafi
|
fea24b88e4
intel: stratix10: Fix reliance on hard coded clock information
|
há 5 anos atrás |
|
Muhammad Hadi Asyrafi Abdul Halim
|
10e70f87e0
intel: Enable watchdog timer on Intel S10 platform
|
há 5 anos atrás |
 Loh Tien Hock
|
9d82ef26c6
plat: intel: Add BL2 support for Stratix 10 SoC
|
há 5 anos atrás |
