Cronologia Commit

Autore SHA1 Messaggio Data
  Sieu Mun Tang b3d2850842 fix(intel): update Agilex5 BL2 init flow and other misc changes 3 mesi fa
  Jit Loon Lim 150d2be0d2 fix(intel): fix hardcoded mpu frequency ticks 1 anno fa
  Sieu Mun Tang 02a9d70c4d feat(intel): implement timer init divider via CPU frequency for N5X 2 anni fa
  Sieu Mun Tang 0d19eda0dd fix(intel): remove unused printout 2 anni fa
  BenjaminLimJL f65bdf3a54 feat(intel): implement timer init divider via cpu frequency. (#1) 2 anni fa
  Tien Hock Loh 811af8b768 plat: intel: Additional instruction required to enable global timer 4 anni fa
  Hadi Asyrafi d8820789ca intel: Platform common code refactor 5 anni fa