Commit History

Author SHA1 Message Date
  Sieu Mun Tang c1253b2445 fix(intel): update Agilex5 warm reset subroutines 1 month ago
  Sieu Mun Tang b3d2850842 fix(intel): update Agilex5 BL2 init flow and other misc changes 3 months ago
  Tanmay Kathpalia 3c640c124e fix(intel): add cache invalidation during BL31 initialization 5 months ago
  Harrison Mutai 998da640fa refactor: fix common misspelling of init* 8 months ago
  Jit Loon Lim cfbac59590 fix(intel): bl31 overwrite OCRAM configuration 1 year ago
  Jit Loon Lim 7931d3322d feat(intel): platform enablement for Agilex5 SoC FPGA 1 year ago