/*
 * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#define GIC_CTRL_ADDR		30000000
#define GIC_GICR_OFFSET		0x1000000
#define UART_OFFSET		0x10000
/* 1440x3200@120 framebuffer */
#define LCD_TIMING_CLK 836000000
#define LCD_TIMING								\
	clock-frequency = <LCD_TIMING_CLK>;					\
	hactive = <1440>;							\
	vactive = <3200>;							\
	hfront-porch = <136>;							\
	hback-porch = <296>;							\
	hsync-len = <160>;							\
	vfront-porch = <3>;							\
	vback-porch = <217>;							\
	vsync-len = <10>

/ {
	chosen {
		stdout-path = "serial0:38400n8";
	};

#if TC_FPGA_ANDROID_IMG_IN_RAM
	reserved-memory {
		phram@0x880000000 {
			/*
			 * starting from 0x8_8000_0000 reserve some memory
			 * android image will be side loaded to this location
			 */
			reg = <0x8 0x80000000  HI(ANDROID_FS_SIZE) LO(ANDROID_FS_SIZE)>
			no-map;
		};
	};
#endif /* TC_FPGA_ANDROID_IMG_IN_RAM */

	ethernet: ethernet@ETHERNET_ADDR {
		compatible = "smsc,lan9115";
		phy-mode = "mii";
	};

	mmci: mmci@MMC_ADDR {
		non-removable;
	};
};