bl1_main.c 7.9 KB

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  1. /*
  2. * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <assert.h>
  7. #include <platform_def.h>
  8. #include <arch.h>
  9. #include <arch_features.h>
  10. #include <arch_helpers.h>
  11. #include <bl1/bl1.h>
  12. #include <common/bl_common.h>
  13. #include <common/debug.h>
  14. #include <drivers/auth/auth_mod.h>
  15. #include <drivers/auth/crypto_mod.h>
  16. #include <drivers/console.h>
  17. #include <lib/cpus/errata_report.h>
  18. #include <lib/utils.h>
  19. #include <plat/common/platform.h>
  20. #include <smccc_helpers.h>
  21. #include <tools_share/uuid.h>
  22. #include "bl1_private.h"
  23. static void bl1_load_bl2(void);
  24. #if ENABLE_PAUTH
  25. uint64_t bl1_apiakey[2];
  26. #endif
  27. /*******************************************************************************
  28. * Helper utility to calculate the BL2 memory layout taking into consideration
  29. * the BL1 RW data assuming that it is at the top of the memory layout.
  30. ******************************************************************************/
  31. void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
  32. meminfo_t *bl2_mem_layout)
  33. {
  34. assert(bl1_mem_layout != NULL);
  35. assert(bl2_mem_layout != NULL);
  36. /*
  37. * Remove BL1 RW data from the scope of memory visible to BL2.
  38. * This is assuming BL1 RW data is at the top of bl1_mem_layout.
  39. */
  40. assert(BL1_RW_BASE > bl1_mem_layout->total_base);
  41. bl2_mem_layout->total_base = bl1_mem_layout->total_base;
  42. bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
  43. flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
  44. }
  45. /*******************************************************************************
  46. * Setup function for BL1.
  47. ******************************************************************************/
  48. void bl1_setup(void)
  49. {
  50. /* Perform early platform-specific setup */
  51. bl1_early_platform_setup();
  52. /* Perform late platform-specific setup */
  53. bl1_plat_arch_setup();
  54. #if CTX_INCLUDE_PAUTH_REGS
  55. /*
  56. * Assert that the ARMv8.3-PAuth registers are present or an access
  57. * fault will be triggered when they are being saved or restored.
  58. */
  59. assert(is_armv8_3_pauth_present());
  60. #endif /* CTX_INCLUDE_PAUTH_REGS */
  61. }
  62. /*******************************************************************************
  63. * Function to perform late architectural and platform specific initialization.
  64. * It also queries the platform to load and run next BL image. Only called
  65. * by the primary cpu after a cold boot.
  66. ******************************************************************************/
  67. void bl1_main(void)
  68. {
  69. unsigned int image_id;
  70. /* Announce our arrival */
  71. NOTICE(FIRMWARE_WELCOME_STR);
  72. NOTICE("BL1: %s\n", version_string);
  73. NOTICE("BL1: %s\n", build_message);
  74. INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
  75. print_errata_status();
  76. #if ENABLE_ASSERTIONS
  77. u_register_t val;
  78. /*
  79. * Ensure that MMU/Caches and coherency are turned on
  80. */
  81. #ifdef __aarch64__
  82. val = read_sctlr_el3();
  83. #else
  84. val = read_sctlr();
  85. #endif
  86. assert((val & SCTLR_M_BIT) != 0);
  87. assert((val & SCTLR_C_BIT) != 0);
  88. assert((val & SCTLR_I_BIT) != 0);
  89. /*
  90. * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
  91. * provided platform value
  92. */
  93. val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
  94. /*
  95. * If CWG is zero, then no CWG information is available but we can
  96. * at least check the platform value is less than the architectural
  97. * maximum.
  98. */
  99. if (val != 0)
  100. assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
  101. else
  102. assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
  103. #endif /* ENABLE_ASSERTIONS */
  104. /* Perform remaining generic architectural setup from EL3 */
  105. bl1_arch_setup();
  106. crypto_mod_init();
  107. /* Initialize authentication module */
  108. auth_mod_init();
  109. /* Initialize the measured boot */
  110. bl1_plat_mboot_init();
  111. /* Perform platform setup in BL1. */
  112. bl1_platform_setup();
  113. #if ENABLE_PAUTH
  114. /* Store APIAKey_EL1 key */
  115. bl1_apiakey[0] = read_apiakeylo_el1();
  116. bl1_apiakey[1] = read_apiakeyhi_el1();
  117. #endif /* ENABLE_PAUTH */
  118. /* Get the image id of next image to load and run. */
  119. image_id = bl1_plat_get_next_image_id();
  120. /*
  121. * We currently interpret any image id other than
  122. * BL2_IMAGE_ID as the start of firmware update.
  123. */
  124. if (image_id == BL2_IMAGE_ID)
  125. bl1_load_bl2();
  126. else
  127. NOTICE("BL1-FWU: *******FWU Process Started*******\n");
  128. /* Teardown the measured boot driver */
  129. bl1_plat_mboot_finish();
  130. bl1_prepare_next_image(image_id);
  131. console_flush();
  132. }
  133. /*******************************************************************************
  134. * This function locates and loads the BL2 raw binary image in the trusted SRAM.
  135. * Called by the primary cpu after a cold boot.
  136. * TODO: Add support for alternative image load mechanism e.g using virtio/elf
  137. * loader etc.
  138. ******************************************************************************/
  139. static void bl1_load_bl2(void)
  140. {
  141. image_desc_t *desc;
  142. image_info_t *info;
  143. int err;
  144. /* Get the image descriptor */
  145. desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
  146. assert(desc != NULL);
  147. /* Get the image info */
  148. info = &desc->image_info;
  149. INFO("BL1: Loading BL2\n");
  150. err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
  151. if (err != 0) {
  152. ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
  153. plat_error_handler(err);
  154. }
  155. err = load_auth_image(BL2_IMAGE_ID, info);
  156. if (err != 0) {
  157. ERROR("Failed to load BL2 firmware.\n");
  158. plat_error_handler(err);
  159. }
  160. /* Allow platform to handle image information. */
  161. err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
  162. if (err != 0) {
  163. ERROR("Failure in post image load handling of BL2 (%d)\n", err);
  164. plat_error_handler(err);
  165. }
  166. NOTICE("BL1: Booting BL2\n");
  167. }
  168. /*******************************************************************************
  169. * Function called just before handing over to the next BL to inform the user
  170. * about the boot progress. In debug mode, also print details about the BL
  171. * image's execution context.
  172. ******************************************************************************/
  173. void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
  174. {
  175. #ifdef __aarch64__
  176. NOTICE("BL1: Booting BL31\n");
  177. #else
  178. NOTICE("BL1: Booting BL32\n");
  179. #endif /* __aarch64__ */
  180. print_entry_point_info(bl_ep_info);
  181. }
  182. #if SPIN_ON_BL1_EXIT
  183. void print_debug_loop_message(void)
  184. {
  185. NOTICE("BL1: Debug loop, spinning forever\n");
  186. NOTICE("BL1: Please connect the debugger to continue\n");
  187. }
  188. #endif
  189. /*******************************************************************************
  190. * Top level handler for servicing BL1 SMCs.
  191. ******************************************************************************/
  192. u_register_t bl1_smc_handler(unsigned int smc_fid,
  193. u_register_t x1,
  194. u_register_t x2,
  195. u_register_t x3,
  196. u_register_t x4,
  197. void *cookie,
  198. void *handle,
  199. unsigned int flags)
  200. {
  201. /* BL1 Service UUID */
  202. DEFINE_SVC_UUID2(bl1_svc_uid,
  203. U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75,
  204. 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
  205. #if TRUSTED_BOARD_BOOT
  206. /*
  207. * Dispatch FWU calls to FWU SMC handler and return its return
  208. * value
  209. */
  210. if (is_fwu_fid(smc_fid)) {
  211. return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
  212. handle, flags);
  213. }
  214. #endif
  215. switch (smc_fid) {
  216. case BL1_SMC_CALL_COUNT:
  217. SMC_RET1(handle, BL1_NUM_SMC_CALLS);
  218. case BL1_SMC_UID:
  219. SMC_UUID_RET(handle, bl1_svc_uid);
  220. case BL1_SMC_VERSION:
  221. SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
  222. default:
  223. WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid);
  224. SMC_RET1(handle, SMC_UNK);
  225. }
  226. }
  227. /*******************************************************************************
  228. * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
  229. * compliance when invoking bl1_smc_handler.
  230. ******************************************************************************/
  231. u_register_t bl1_smc_wrapper(uint32_t smc_fid,
  232. void *cookie,
  233. void *handle,
  234. unsigned int flags)
  235. {
  236. u_register_t x1, x2, x3, x4;
  237. assert(handle != NULL);
  238. get_smc_params_from_ctx(handle, x1, x2, x3, x4);
  239. return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
  240. }