stm32mp15xx-dhcom-som.dtsi 6.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336
  1. // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
  4. * Copyright (C) 2022 DH electronics GmbH
  5. */
  6. #include "stm32mp15-pinctrl.dtsi"
  7. #include "stm32mp15xxaa-pinctrl.dtsi"
  8. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  9. #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  10. / {
  11. memory@c0000000 {
  12. device_type = "memory";
  13. reg = <0xC0000000 0x40000000>;
  14. };
  15. };
  16. &bsec {
  17. board_id: board_id@ec {
  18. reg = <0xec 0x4>;
  19. st,non-secure-otp;
  20. };
  21. };
  22. &cpu0 {
  23. cpu-supply = <&vddcore>;
  24. };
  25. &cpu1 {
  26. cpu-supply = <&vddcore>;
  27. };
  28. &hash1 {
  29. status = "okay";
  30. };
  31. &i2c4 {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&i2c4_pins_a>;
  34. i2c-scl-rising-time-ns = <185>;
  35. i2c-scl-falling-time-ns = <20>;
  36. status = "okay";
  37. pmic: stpmic@33 {
  38. compatible = "st,stpmic1";
  39. reg = <0x33>;
  40. interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
  41. interrupt-controller;
  42. #interrupt-cells = <2>;
  43. status = "okay";
  44. regulators {
  45. compatible = "st,stpmic1-regulators";
  46. ldo1-supply = <&v3v3>;
  47. ldo2-supply = <&v3v3>;
  48. ldo3-supply = <&vdd_ddr>;
  49. ldo5-supply = <&v3v3>;
  50. ldo6-supply = <&v3v3>;
  51. pwr_sw1-supply = <&bst_out>;
  52. pwr_sw2-supply = <&bst_out>;
  53. vddcore: buck1 {
  54. regulator-name = "vddcore";
  55. regulator-min-microvolt = <1200000>;
  56. regulator-max-microvolt = <1350000>;
  57. regulator-always-on;
  58. regulator-initial-mode = <0>;
  59. regulator-over-current-protection;
  60. };
  61. vdd_ddr: buck2 {
  62. regulator-name = "vdd_ddr";
  63. regulator-min-microvolt = <1350000>;
  64. regulator-max-microvolt = <1350000>;
  65. regulator-always-on;
  66. regulator-initial-mode = <0>;
  67. regulator-over-current-protection;
  68. };
  69. vdd: buck3 {
  70. regulator-name = "vdd";
  71. regulator-min-microvolt = <3300000>;
  72. regulator-max-microvolt = <3300000>;
  73. regulator-always-on;
  74. st,mask-reset;
  75. regulator-initial-mode = <0>;
  76. regulator-over-current-protection;
  77. };
  78. v3v3: buck4 {
  79. regulator-name = "v3v3";
  80. regulator-min-microvolt = <3300000>;
  81. regulator-max-microvolt = <3300000>;
  82. regulator-always-on;
  83. regulator-over-current-protection;
  84. regulator-initial-mode = <0>;
  85. };
  86. vdda: ldo1 {
  87. regulator-name = "vdda";
  88. regulator-min-microvolt = <2900000>;
  89. regulator-max-microvolt = <2900000>;
  90. regulator-always-on;
  91. };
  92. v2v8: ldo2 {
  93. regulator-name = "v2v8";
  94. regulator-min-microvolt = <2800000>;
  95. regulator-max-microvolt = <2800000>;
  96. };
  97. vtt_ddr: ldo3 {
  98. regulator-name = "vtt_ddr";
  99. regulator-always-on;
  100. regulator-over-current-protection;
  101. st,regulator-sink-source;
  102. };
  103. vdd_usb: ldo4 {
  104. regulator-name = "vdd_usb";
  105. regulator-min-microvolt = <3300000>;
  106. regulator-max-microvolt = <3300000>;
  107. };
  108. vdd_sd: ldo5 {
  109. regulator-name = "vdd_sd";
  110. regulator-min-microvolt = <2900000>;
  111. regulator-max-microvolt = <2900000>;
  112. regulator-boot-on;
  113. };
  114. v1v8: ldo6 {
  115. regulator-name = "v1v8";
  116. regulator-min-microvolt = <1800000>;
  117. regulator-max-microvolt = <1800000>;
  118. };
  119. vref_ddr: vref_ddr {
  120. regulator-name = "vref_ddr";
  121. regulator-always-on;
  122. };
  123. bst_out: boost {
  124. regulator-name = "bst_out";
  125. };
  126. vbus_otg: pwr_sw1 {
  127. regulator-name = "vbus_otg";
  128. };
  129. vbus_sw: pwr_sw2 {
  130. regulator-name = "vbus_sw";
  131. regulator-active-discharge = <1>;
  132. };
  133. };
  134. };
  135. };
  136. &iwdg2 {
  137. timeout-sec = <32>;
  138. status = "okay";
  139. };
  140. &pwr_regulators {
  141. vdd-supply = <&vdd>;
  142. vdd_3v3_usbfs-supply = <&vdd_usb>;
  143. };
  144. &qspi {
  145. pinctrl-names = "default";
  146. pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
  147. reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. status = "okay";
  151. flash0: flash@0 {
  152. compatible = "jedec,spi-nor";
  153. reg = <0>;
  154. spi-rx-bus-width = <4>;
  155. spi-max-frequency = <108000000>;
  156. #address-cells = <1>;
  157. #size-cells = <1>;
  158. };
  159. };
  160. &rcc {
  161. st,clksrc = <
  162. CLK_MPU_PLL1P
  163. CLK_AXI_PLL2P
  164. CLK_MCU_PLL3P
  165. CLK_PLL12_HSE
  166. CLK_PLL3_HSE
  167. CLK_PLL4_HSE
  168. CLK_RTC_LSE
  169. CLK_MCO1_DISABLED
  170. CLK_MCO2_PLL4P
  171. >;
  172. st,clkdiv = <
  173. 1 /*MPU*/
  174. 0 /*AXI*/
  175. 0 /*MCU*/
  176. 1 /*APB1*/
  177. 1 /*APB2*/
  178. 1 /*APB3*/
  179. 1 /*APB4*/
  180. 2 /*APB5*/
  181. 23 /*RTC*/
  182. 0 /*MCO1*/
  183. 1 /*MCO2*/
  184. >;
  185. st,pkcs = <
  186. CLK_CKPER_HSE
  187. CLK_FMC_ACLK
  188. CLK_QSPI_ACLK
  189. CLK_ETH_PLL4P
  190. CLK_SDMMC12_PLL4P
  191. CLK_DSI_DSIPLL
  192. CLK_STGEN_HSE
  193. CLK_USBPHY_HSE
  194. CLK_SPI2S1_PLL3Q
  195. CLK_SPI2S23_PLL3Q
  196. CLK_SPI45_HSI
  197. CLK_SPI6_HSI
  198. CLK_I2C46_HSI
  199. CLK_SDMMC3_PLL4P
  200. CLK_USBO_USBPHY
  201. CLK_ADC_CKPER
  202. CLK_CEC_LSE
  203. CLK_I2C12_HSI
  204. CLK_I2C35_HSI
  205. CLK_UART1_HSI
  206. CLK_UART24_HSI
  207. CLK_UART35_HSI
  208. CLK_UART6_HSI
  209. CLK_UART78_HSI
  210. CLK_SPDIF_PLL4P
  211. CLK_FDCAN_PLL4R
  212. CLK_SAI1_PLL3Q
  213. CLK_SAI2_PLL3Q
  214. CLK_SAI3_PLL3Q
  215. CLK_SAI4_PLL3Q
  216. CLK_RNG1_LSI
  217. CLK_RNG2_LSI
  218. CLK_LPTIM1_PCLK1
  219. CLK_LPTIM23_PCLK3
  220. CLK_LPTIM45_LSE
  221. >;
  222. /* VCO = 1300.0 MHz => P = 650 (CPU) */
  223. pll1: st,pll@0 {
  224. compatible = "st,stm32mp1-pll";
  225. reg = <0>;
  226. cfg = <2 80 0 0 0 PQR(1,0,0)>;
  227. frac = <0x800>;
  228. };
  229. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  230. pll2: st,pll@1 {
  231. compatible = "st,stm32mp1-pll";
  232. reg = <1>;
  233. cfg = <2 65 1 0 0 PQR(1,1,1)>;
  234. frac = <0x1400>;
  235. };
  236. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  237. pll3: st,pll@2 {
  238. compatible = "st,stm32mp1-pll";
  239. reg = <2>;
  240. cfg = <1 33 1 16 36 PQR(1,1,1)>;
  241. frac = <0x1a04>;
  242. };
  243. /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
  244. pll4: st,pll@3 {
  245. compatible = "st,stm32mp1-pll";
  246. reg = <3>;
  247. cfg = <1 49 5 11 11 PQR(1,1,1)>;
  248. };
  249. };
  250. &rng1 {
  251. status = "okay";
  252. };
  253. &rtc {
  254. status = "okay";
  255. };
  256. &sdmmc1 {
  257. pinctrl-names = "default";
  258. pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
  259. disable-wp;
  260. st,sig-dir;
  261. st,neg-edge;
  262. bus-width = <4>;
  263. vmmc-supply = <&vdd_sd>;
  264. status = "okay";
  265. };
  266. &sdmmc1_b4_pins_a {
  267. /*
  268. * SD bus pull-up resistors:
  269. * - optional on SoMs with SD voltage translator
  270. * - mandatory on SoMs without SD voltage translator
  271. */
  272. pins1 {
  273. bias-pull-up;
  274. };
  275. pins2 {
  276. bias-pull-up;
  277. };
  278. };
  279. &sdmmc2 {
  280. pinctrl-names = "default";
  281. pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
  282. non-removable;
  283. no-sd;
  284. no-sdio;
  285. st,neg-edge;
  286. bus-width = <8>;
  287. vmmc-supply = <&v3v3>;
  288. vqmmc-supply = <&v3v3>;
  289. mmc-ddr-3_3v;
  290. status = "okay";
  291. };
  292. &uart4 {
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&uart4_pins_a>;
  295. status = "okay";
  296. };