phy-porting-layer.h 3.0 KB

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  1. /*
  2. * Copyright (C) 2021 Sartura Ltd.
  3. * Copyright (C) 2021 Globalscale technologies, Inc.
  4. * Copyright (C) 2021 Marvell International Ltd.
  5. *
  6. * SPDX-License-Identifier: BSD-3-Clause
  7. * https://spdx.org/licenses
  8. */
  9. #ifndef __PHY_PORTING_LAYER_H
  10. #define __PHY_PORTING_LAYER_H
  11. #define MAX_LANE_NR 6
  12. static const struct xfi_params
  13. xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
  14. /* AP0 */
  15. {
  16. /* CP 0 */
  17. {
  18. { 0 }, /* Comphy0 */
  19. { 0 }, /* Comphy1 */
  20. { 0 }, /* Comphy2 */
  21. { 0 }, /* Comphy3 */
  22. { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x60,
  23. .g1_dfe_res = 0x1, .g1_amp = 0x1c, .g1_emph = 0xe,
  24. .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x1,
  25. .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
  26. .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
  27. .valid = 1 }, /* Comphy4 */
  28. { 0 }, /* Comphy5 */
  29. },
  30. },
  31. };
  32. static const struct sata_params
  33. sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
  34. /* AP0 */
  35. {
  36. /* CP 0 */
  37. {
  38. { 0 }, /* Comphy0 */
  39. { 0 }, /* Comphy1 */
  40. { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
  41. .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
  42. .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1,
  43. .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1,
  44. .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0,
  45. .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1,
  46. .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf,
  47. .align90 = 0x61,
  48. .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3,
  49. .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3,
  50. .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2,
  51. .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, .g3_rx_selmupi = 0x2,
  52. .polarity_invert = COMPHY_POLARITY_NO_INVERT,
  53. .valid = 0x1
  54. }, /* Comphy2 */
  55. { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
  56. .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
  57. .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1,
  58. .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1,
  59. .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0,
  60. .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1,
  61. .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf,
  62. .align90 = 0x61,
  63. .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3,
  64. .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3,
  65. .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2,
  66. .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, .g3_rx_selmupi = 0x2,
  67. .polarity_invert = COMPHY_POLARITY_NO_INVERT,
  68. .valid = 0x1
  69. }, /* Comphy3 */
  70. { 0 }, /* Comphy4 */
  71. { 0 }, /* Comphy5 */
  72. },
  73. },
  74. };
  75. static const struct usb_params
  76. usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
  77. [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
  78. .polarity_invert = COMPHY_POLARITY_NO_INVERT
  79. },
  80. };
  81. #endif /* __PHY_PORTING_LAYER_H */