dram_port.c 4.1 KB

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  1. /*
  2. * Copyright (C) 2018 Marvell International Ltd.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. * https://spdx.org/licenses
  6. */
  7. #include <arch_helpers.h>
  8. #include <common/debug.h>
  9. #include <drivers/mentor/mi2cv.h>
  10. #include <lib/mmio.h>
  11. #include <mv_ddr_if.h>
  12. #include <mvebu_def.h>
  13. #include <plat_marvell.h>
  14. #define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0)
  15. #define MVEBU_AP_MPP_CTRL4_OFFS 16
  16. #define MVEBU_AP_MPP_CTRL5_OFFS 20
  17. #define MVEBU_AP_MPP_CTRL4_I2C0_SDA_ENA 0x3
  18. #define MVEBU_AP_MPP_CTRL5_I2C0_SCK_ENA 0x3
  19. #define MVEBU_CP_MPP_CTRL37_OFFS 20
  20. #define MVEBU_CP_MPP_CTRL38_OFFS 24
  21. #define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2
  22. #define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2
  23. #define MVEBU_MPP_CTRL_MASK 0xf
  24. /*
  25. * This struct provides the DRAM training code with
  26. * the appropriate board DRAM configuration
  27. */
  28. static struct mv_ddr_topology_map board_topology_map = {
  29. /* MISL board with 1CS 8Gb x4 devices of Micron 2400T */
  30. DEBUG_LEVEL_ERROR,
  31. 0x1, /* active interfaces */
  32. /* cs_mask, mirror, dqs_swap, ck_swap X subphys */
  33. { { { {0x1, 0x0, 0, 0}, /* FIXME: change the cs mask for all 64 bit */
  34. {0x1, 0x0, 0, 0},
  35. {0x1, 0x0, 0, 0},
  36. {0x1, 0x0, 0, 0},
  37. {0x1, 0x0, 0, 0},
  38. {0x1, 0x0, 0, 0},
  39. {0x1, 0x0, 0, 0},
  40. {0x1, 0x0, 0, 0},
  41. {0x1, 0x0, 0, 0} },
  42. /* TODO: double check if the speed bin is 2400T */
  43. SPEED_BIN_DDR_2400T, /* speed_bin */
  44. MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
  45. MV_DDR_DIE_CAP_8GBIT, /* die capacity */
  46. MV_DDR_FREQ_SAR, /* frequency */
  47. 0, 0, /* cas_l, cas_wl */
  48. MV_DDR_TEMP_LOW} }, /* temperature */
  49. #if DDR32
  50. MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
  51. #else
  52. MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
  53. #endif
  54. MV_DDR_CFG_SPD, /* ddr configuration data source */
  55. NOT_COMBINED, /* ddr twin-die combined*/
  56. { {0} }, /* raw spd data */
  57. {0}, /* timing parameters */
  58. { /* electrical configuration */
  59. { /* memory electrical configuration */
  60. MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
  61. {
  62. MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
  63. MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
  64. },
  65. {
  66. MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
  67. MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
  68. },
  69. MV_DDR_DIC_RZQ_DIV7 /* dic */
  70. },
  71. { /* phy electrical configuration */
  72. MV_DDR_OHM_30, /* data_drv_p */
  73. MV_DDR_OHM_30, /* data_drv_n */
  74. MV_DDR_OHM_30, /* ctrl_drv_p */
  75. MV_DDR_OHM_30, /* ctrl_drv_n */
  76. {
  77. MV_DDR_OHM_60, /* odt_p 1cs */
  78. MV_DDR_OHM_120 /* odt_p 2cs */
  79. },
  80. {
  81. MV_DDR_OHM_60, /* odt_n 1cs */
  82. MV_DDR_OHM_120 /* odt_n 2cs */
  83. },
  84. },
  85. { /* mac electrical configuration */
  86. MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
  87. MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
  88. MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
  89. },
  90. }
  91. };
  92. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  93. {
  94. /* Return the board topology as defined in the board code */
  95. return &board_topology_map;
  96. }
  97. static void mpp_config(void)
  98. {
  99. uintptr_t reg;
  100. uint32_t val;
  101. reg = MVEBU_CP_MPP_REGS(0, 4);
  102. /* configure CP0 MPP 37 and 38 to i2c */
  103. val = mmio_read_32(reg);
  104. val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) |
  105. (MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS));
  106. val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA <<
  107. MVEBU_CP_MPP_CTRL37_OFFS) |
  108. (MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA <<
  109. MVEBU_CP_MPP_CTRL38_OFFS);
  110. mmio_write_32(reg, val);
  111. }
  112. /*
  113. * This function may modify the default DRAM parameters
  114. * based on information received from SPD or bootloader
  115. * configuration located on non volatile storage
  116. */
  117. void plat_marvell_dram_update_topology(void)
  118. {
  119. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  120. INFO("Gathering DRAM information\n");
  121. if (tm->cfg_src == MV_DDR_CFG_SPD) {
  122. /* configure MPPs to enable i2c */
  123. mpp_config();
  124. /* initialize i2c */
  125. i2c_init((void *)MVEBU_CP0_I2C_BASE);
  126. /* select SPD memory page 0 to access DRAM configuration */
  127. i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 0);
  128. /* read data from spd */
  129. i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
  130. sizeof(tm->spd_data.all_bytes));
  131. }
  132. }