marvell_plat_config.c 5.2 KB

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  1. /*
  2. * Copyright (C) 2018 Marvell International Ltd.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. * https://spdx.org/licenses
  6. */
  7. #include <drivers/delay_timer.h>
  8. #include <lib/mmio.h>
  9. #include <armada_common.h>
  10. /*
  11. * If bootrom is currently at BLE there's no need to include the memory
  12. * maps structure at this point
  13. */
  14. #include <mvebu_def.h>
  15. #ifndef IMAGE_BLE
  16. /*****************************************************************************
  17. * GPIO Configuration
  18. *****************************************************************************
  19. */
  20. #define MPP_CONTROL_REGISTER 0xf2440018
  21. #define MPP_CONTROL_MPP_SEL_52_MASK 0xf0000
  22. #define GPIO_DATA_OUT1_REGISTER 0xf2440140
  23. #define GPIO_DATA_OUT_EN_CTRL1_REGISTER 0xf2440144
  24. #define GPIO52_MASK 0x100000
  25. /* Reset PCIe via GPIO number 52 */
  26. int marvell_gpio_config(void)
  27. {
  28. uint32_t reg;
  29. reg = mmio_read_32(MPP_CONTROL_REGISTER);
  30. reg |= MPP_CONTROL_MPP_SEL_52_MASK;
  31. mmio_write_32(MPP_CONTROL_REGISTER, reg);
  32. reg = mmio_read_32(GPIO_DATA_OUT1_REGISTER);
  33. reg |= GPIO52_MASK;
  34. mmio_write_32(GPIO_DATA_OUT1_REGISTER, reg);
  35. reg = mmio_read_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER);
  36. reg &= ~GPIO52_MASK;
  37. mmio_write_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER, reg);
  38. udelay(100);
  39. return 0;
  40. }
  41. /*****************************************************************************
  42. * AMB Configuration
  43. *****************************************************************************
  44. */
  45. struct addr_map_win amb_memory_map[] = {
  46. /* CP1 SPI1 CS0 Direct Mode access */
  47. {0xf900, 0x1000000, AMB_SPI1_CS0_ID},
  48. };
  49. int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
  50. uintptr_t base)
  51. {
  52. *win = amb_memory_map;
  53. if (*win == NULL)
  54. *size = 0;
  55. else
  56. *size = ARRAY_SIZE(amb_memory_map);
  57. return 0;
  58. }
  59. #endif
  60. /*****************************************************************************
  61. * IO WIN Configuration
  62. *****************************************************************************
  63. */
  64. struct addr_map_win io_win_memory_map[] = {
  65. /* CP1 (MCI0) internal regs */
  66. {0x00000000f4000000, 0x2000000, MCI_0_TID},
  67. #ifndef IMAGE_BLE
  68. /* PCIe0-2 and SPI1_CS0 (RUNIT) on CP1*/
  69. {0x00000000f9000000, 0x4000000, MCI_0_TID},
  70. /* MCI 0 indirect window */
  71. {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
  72. /* MCI 1 indirect window */
  73. {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
  74. #endif
  75. };
  76. uint32_t marvell_get_io_win_gcr_target(int ap_index)
  77. {
  78. return PIDI_TID;
  79. }
  80. int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
  81. uint32_t *size)
  82. {
  83. *win = io_win_memory_map;
  84. if (*win == NULL)
  85. *size = 0;
  86. else
  87. *size = ARRAY_SIZE(io_win_memory_map);
  88. return 0;
  89. }
  90. #ifndef IMAGE_BLE
  91. /*****************************************************************************
  92. * IOB Configuration
  93. *****************************************************************************
  94. */
  95. struct addr_map_win iob_memory_map_cp0[] = {
  96. /* CP0 */
  97. /* PEX1_X1 window */
  98. {0x00000000f7000000, 0x1000000, PEX1_TID},
  99. /* PEX2_X1 window */
  100. {0x00000000f8000000, 0x1000000, PEX2_TID},
  101. /* PEX0_X4 window */
  102. {0x00000000f6000000, 0x1000000, PEX0_TID},
  103. {0x00000000c0000000, 0x30000000, PEX0_TID},
  104. {0x0000000800000000, 0x100000000, PEX0_TID},
  105. };
  106. struct addr_map_win iob_memory_map_cp1[] = {
  107. /* CP1 */
  108. /* SPI1_CS0 (RUNIT) window */
  109. {0x00000000f9000000, 0x1000000, RUNIT_TID},
  110. /* PEX1_X1 window */
  111. {0x00000000fb000000, 0x1000000, PEX1_TID},
  112. /* PEX2_X1 window */
  113. {0x00000000fc000000, 0x1000000, PEX2_TID},
  114. /* PEX0_X4 window */
  115. {0x00000000fa000000, 0x1000000, PEX0_TID}
  116. };
  117. int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
  118. uintptr_t base)
  119. {
  120. switch (base) {
  121. case MVEBU_CP_REGS_BASE(0):
  122. *win = iob_memory_map_cp0;
  123. *size = ARRAY_SIZE(iob_memory_map_cp0);
  124. return 0;
  125. case MVEBU_CP_REGS_BASE(1):
  126. *win = iob_memory_map_cp1;
  127. *size = ARRAY_SIZE(iob_memory_map_cp1);
  128. return 0;
  129. default:
  130. *size = 0;
  131. *win = 0;
  132. return 1;
  133. }
  134. }
  135. #endif
  136. /*****************************************************************************
  137. * CCU Configuration
  138. *****************************************************************************
  139. */
  140. struct addr_map_win ccu_memory_map[] = {
  141. #ifdef IMAGE_BLE
  142. {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
  143. #else
  144. #if LLC_SRAM
  145. /* This entry is prepared for OP-TEE OS that enables the LLC SRAM
  146. * and changes the window target to SRAM_TID.
  147. */
  148. {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
  149. #endif
  150. {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
  151. {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
  152. {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
  153. #endif
  154. };
  155. uint32_t marvell_get_ccu_gcr_target(int ap)
  156. {
  157. return DRAM_0_TID;
  158. }
  159. int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
  160. uint32_t *size)
  161. {
  162. *win = ccu_memory_map;
  163. *size = ARRAY_SIZE(ccu_memory_map);
  164. return 0;
  165. }
  166. /* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
  167. /*****************************************************************************
  168. * SKIP IMAGE Configuration
  169. *****************************************************************************
  170. */
  171. void *plat_marvell_get_skip_image_data(void)
  172. {
  173. /* No recovery button on A8k-MCBIN board */
  174. return NULL;
  175. }