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mediatek
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drivers
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vcp
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mt8196
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vcp_reg.h

vcp_reg.h 4.0 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2024, MediaTek Inc. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef VCP_REG_H
    8. 

  8. #define VCP_REG_H
    9. 

  9. 

  10. #include <platform_def.h>
    11. 

  11. 

  12. #define MTK_VCP_REG_BASE		(IO_PHYS + 0x21800000)
    13. 

  13. #define MTK_VCP_REG_BANK_SIZE		(0x1000)
    14. 

  14. 

  15. /*******************************************************************************
    16. 

  16.  * VCP power related setting
    17. 

  17.  ******************************************************************************/
    18. 

  18. #define VCP_POWER_STATUS		(0xE60)
    19. 

  19. #define MMUP_PWR_STA_BIT		(30)
    20. 

  20. #define MMUP_PWR_STA_EN			((uint32_t)(0x3))
    21. 

  21. 

  22. /*******************************************************************************
    23. 

  23.  * VCP registers
    24. 

  24.  ******************************************************************************/
    25. 

  25. /* cfgreg */
    26. 

  26. #define VCP_R_CFGREG			(MTK_VCP_REG_BASE + 0x3d0000)
    27. 

  27. 

  28. #define VCP_R_CORE0_SW_RSTN_CLR		(VCP_R_CFGREG + 0x0000)
    29. 

  29. #define VCP_R_CORE0_SW_RSTN_SET		(VCP_R_CFGREG + 0x0004)
    30. 

  30. #define VCP_R_CORE1_SW_RSTN_CLR		(VCP_R_CFGREG + 0x0008)
    31. 

  31. #define VCP_R_CORE1_SW_RSTN_SET		(VCP_R_CFGREG + 0x000c)
    32. 

  32. #define VCP_R_GIPC_IN_SET		(VCP_R_CFGREG + 0x0028)
    33. 

  33. #define VCP_R_GIPC_IN_CLR		(VCP_R_CFGREG + 0x002c)
    34. 

  34. #define B_GIPC3_SETCLR_1		BIT(13)
    35. 

  35. 

  36. /* cfgreg_core0 */
    37. 

  37. #define VCP_R_CFGREG_CORE0		(MTK_VCP_REG_BASE + 0x20a000)
    38. 

  38. 

  39. #define VCP_R_CORE0_STATUS		(VCP_R_CFGREG_CORE0 + 0x0070)
    40. 

  40. 

  41. #define CORE0_R_GPR5			(VCP_R_CFGREG_CORE0 + 0x0054)
    42. 

  42. #define VCP_GPR_C0_H0_REBOOT		CORE0_R_GPR5
    43. 

  43. #define CORE0_R_GPR6			(VCP_R_CFGREG_CORE0 + 0x0058)
    44. 

  44. #define VCP_GPR_C0_H1_REBOOT		CORE0_R_GPR6
    45. 

  45. #define VCP_CORE_RDY_TO_REBOOT		(0x34)
    46. 

  46. #define VCP_CORE_REBOOT_OK		BIT(0)
    47. 

  47. 

  48. /* cfgreg_core1 */
    49. 

  49. #define VCP_R_CFGREG_CORE1		(MTK_VCP_REG_BASE + 0x20d000)
    50. 

  50. 

  51. #define VCP_R_CORE1_STATUS		(VCP_R_CFGREG_CORE1 + 0x0070)
    52. 

  52. #define CORE1_R_GPR5			(VCP_R_CFGREG_CORE1 + 0x0054)
    53. 

  53. #define VCP_GPR_CORE1_REBOOT		CORE1_R_GPR5
    54. 

  54. 

  55. /* sec */
    56. 

  56. #define VCP_R_SEC_CTRL			(MTK_VCP_REG_BASE + 0x270000)
    57. 

  57. #define VCP_OFFSET_ENABLE_P		BIT(13)
    58. 

  58. #define VCP_OFFSET_ENABLE_B		BIT(12)
    59. 

  59. #define VCP_R_SEC_CTRL_2		(VCP_R_SEC_CTRL + 0x0004)
    60. 

  60. #define CORE0_SEC_BIT_SEL		BIT(0)
    61. 

  61. #define CORE1_SEC_BIT_SEL		BIT(8)
    62. 

  62. #define VCP_GPR0_CFGREG_SEC		(VCP_R_SEC_CTRL + 0x0040)
    63. 

  63. #define VCP_GPR1_CFGREG_SEC		(VCP_R_SEC_CTRL + 0x0044)
    64. 

  64. #define VCP_GPR2_CFGREG_SEC		(VCP_R_SEC_CTRL + 0x0048)
    65. 

  65. #define VCP_GPR3_CFGREG_SEC		(VCP_R_SEC_CTRL + 0x004C)
    66. 

  66. #define VCP_R_SEC_DOMAIN		(VCP_R_SEC_CTRL + 0x0080)
    67. 

  67. #define VCP_DOMAIN_ID			U(13)
    68. 

  68. #define VCP_DOMAIN_MASK			U(0xF)
    69. 

  69. #define VCP_CORE0_TH0_PM_AXI_DOMAIN	(0)
    70. 

  70. #define VCP_CORE0_TH0_DM_AXI_DOMAIN	(4)
    71. 

  71. #define VCP_S_DMA0_DOMAIN		(12)
    72. 

  72. #define VCP_HWCCF_DOMAIN		(16)
    73. 

  73. #define VCP_CORE0_TH1_PM_AXI_DOMAIN	(20)
    74. 

  74. #define VCP_CORE0_TH1_DM_AXI_DOMAIN	(24)
    75. 

  75. #define VCP_DOMAIN_SET			((VCP_DOMAIN_ID << VCP_CORE0_TH0_PM_AXI_DOMAIN) | \
    76. 

  76. 					 (VCP_DOMAIN_ID << VCP_CORE0_TH0_DM_AXI_DOMAIN) | \
    77. 

  77. 					 (VCP_DOMAIN_ID << VCP_CORE0_TH1_PM_AXI_DOMAIN) | \
    78. 

  78. 					 (VCP_DOMAIN_ID << VCP_CORE0_TH1_DM_AXI_DOMAIN) | \
    79. 

  79. 					 (VCP_DOMAIN_ID << VCP_S_DMA0_DOMAIN))
    80. 

  80. #define VCP_R_SEC_DOMAIN_MMPC		(VCP_R_SEC_CTRL + 0x0084)
    81. 

  81. #define VCP_CORE_MMPC_PM_AXI_DOMAIN	(0)
    82. 

  82. #define VCP_CORE_MMPC_DM_AXI_DOMAIN	(4)
    83. 

  83. #define VCP_DOMAIN_SET_MMPC		((VCP_DOMAIN_ID << VCP_CORE_MMPC_PM_AXI_DOMAIN) | \
    84. 

  84. 					(VCP_DOMAIN_ID << VCP_CORE_MMPC_DM_AXI_DOMAIN))
    85. 

  85. #define R_L2TCM_OFFSET_RANGE_0_LOW	(VCP_R_SEC_CTRL + 0x00B0)
    86. 

  86. #define R_L2TCM_OFFSET_RANGE_0_HIGH	(VCP_R_SEC_CTRL + 0x00B4)
    87. 

  87. #define R_L2TCM_OFFSET			(VCP_R_SEC_CTRL + 0x00D0)
    88. 

  88. #define VCP_R_DYN_SECURE		(VCP_R_SEC_CTRL + 0x01d0)
    89. 

  89. #define VCP_NS_I0			BIT(4)
    90. 

  90. #define VCP_NS_D0			BIT(6)
    91. 

  91. #define VCP_NS_SECURE_B_REGION_ENABLE	(24)
    92. 

  92. #define RESET_NS_SECURE_B_REGION	U(0xFF)
    93. 

  93. #define VCP_R_DYN_SECURE_TH1		(VCP_R_SEC_CTRL + 0x01d4)
    94. 

  94. #define VCP_NS_I1			BIT(5)
    95. 

  95. #define VCP_NS_D1			BIT(7)
    96. 

  96. #define VCP_R_S_DOM_EN0_31		(VCP_R_SEC_CTRL + 0x0200)
    97. 

  97. #define VCP_R_S_DOM_EN32_63		(VCP_R_SEC_CTRL + 0x0204)
    98. 

  98. #define VCP_R_NS_DOM_EN0_31		(VCP_R_SEC_CTRL + 0x0208)
    99. 

  99. #define VCP_R_NS_DOM_EN32_63		(VCP_R_SEC_CTRL + 0x020c)
    100. 

  100. /* IOMMU */
    101. 

  101. #define VCP_R_AXIOMMUEN_DEV_APC		(VCP_R_SEC_CTRL + 0x0088)
    102. 

  102. #define VCP_R_CFG_DEVAPC_AO_BASE	(MTK_VCP_REG_BASE + 0x2d0000)
    103. 

  103. 

  104. #endif /* VCP_REG_H */
    105.