mt_spm_rc_syspll.c 4.8 KB

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  1. /*
  2. * Copyright (c) 2022, MediaTek Inc. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <arch_helpers.h>
  7. #include <common/debug.h>
  8. #include <mt_lp_rm.h>
  9. #include <mt_spm.h>
  10. #include <mt_spm_cond.h>
  11. #include <mt_spm_conservation.h>
  12. #include <mt_spm_constraint.h>
  13. #include <mt_spm_idle.h>
  14. #include <mt_spm_internal.h>
  15. #include <mt_spm_notifier.h>
  16. #include <mt_spm_rc_internal.h>
  17. #include <mt_spm_reg.h>
  18. #include <mt_spm_resource_req.h>
  19. #include <mt_spm_suspend.h>
  20. #include <plat_mtk_lpm.h>
  21. #include <plat_pm.h>
  22. #define CONSTRAINT_SYSPLL_ALLOW \
  23. (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
  24. MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
  25. MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
  26. MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
  27. #if (MTK_SPM_EXTENSION_PMIC_CONTROL == 6362)
  28. #define SPM_FLAG_EXTRA_PMIC_CONTROL (SPM_FLAG_ENABLE_6362_CTRL)
  29. #else
  30. #define SPM_FLAG_EXTRA_PMIC_CONTROL (SPM_FLAG_ENABLE_6315_CTRL)
  31. #endif
  32. #define CONSTRAINT_SYSPLL_PCM_FLAG \
  33. (SPM_FLAG_DISABLE_INFRA_PDN | \
  34. SPM_FLAG_DISABLE_VCORE_DVS | \
  35. SPM_FLAG_DISABLE_VCORE_DFS | \
  36. SPM_FLAG_USE_SRCCLKENO2 | \
  37. SPM_FLAG_SRAM_SLEEP_CTRL | \
  38. SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
  39. SPM_FLAG_USE_SRCCLKENO2)
  40. #define CONSTRAINT_SYSPLL_PCM_FLAG1 (0U)
  41. #define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
  42. static struct mt_spm_cond_tables cond_syspll = {
  43. .name = "syspll",
  44. .table_cg = {
  45. 0x0385E03C, /* MTCMOS1 */
  46. 0x003F0100, /* INFRA0 */
  47. 0x08040802, /* INFRA1 */
  48. 0x06015641, /* INFRA2 */
  49. 0x00000000, /* INFRA3 */
  50. 0x00000000, /* INFRA4 */
  51. 0x00000000, /* INFRA5 */
  52. 0x03720820, /* MMSYS0 */
  53. 0x00000000, /* MMSYS1 */
  54. 0x00000000, /* MMSYS2 */
  55. 0x00015151, /* MMSYS3 */
  56. },
  57. .table_pll = 0U,
  58. };
  59. static struct mt_spm_cond_tables cond_syspll_res = {
  60. .table_cg = {0U},
  61. .table_pll = 0U,
  62. };
  63. static struct constraint_status status = {
  64. .id = MT_RM_CONSTRAINT_ID_SYSPLL,
  65. .valid = (MT_SPM_RC_VALID_SW |
  66. MT_SPM_RC_VALID_COND_LATCH |
  67. MT_SPM_RC_VALID_XSOC_BBLPM),
  68. .cond_block = 0U,
  69. .enter_cnt = 0U,
  70. .cond_res = &cond_syspll_res,
  71. };
  72. static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
  73. unsigned int *resource_req)
  74. {
  75. spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
  76. spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
  77. *resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
  78. }
  79. bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
  80. {
  81. (void)cpu;
  82. (void)state_id;
  83. return ((status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid));
  84. }
  85. int spm_update_rc_syspll(int state_id, int type, const void *val)
  86. {
  87. const struct mt_spm_cond_tables *tlb;
  88. const struct mt_spm_cond_tables *tlb_check;
  89. int res = MT_RM_STATUS_OK;
  90. if (val == NULL) {
  91. res = MT_RM_STATUS_BAD;
  92. } else {
  93. if (type == PLAT_RC_UPDATE_CONDITION) {
  94. tlb = (const struct mt_spm_cond_tables *)val;
  95. tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
  96. status.cond_block =
  97. mt_spm_cond_check(state_id, tlb, tlb_check,
  98. ((status.valid &
  99. MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
  100. (&cond_syspll_res) : (NULL));
  101. } else {
  102. res = MT_RM_STATUS_BAD;
  103. }
  104. }
  105. return res;
  106. }
  107. unsigned int spm_allow_rc_syspll(int state_id)
  108. {
  109. (void)state_id;
  110. return CONSTRAINT_SYSPLL_ALLOW;
  111. }
  112. int spm_run_rc_syspll(unsigned int cpu, int state_id)
  113. {
  114. unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
  115. unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
  116. (void)cpu;
  117. if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
  118. #ifdef MT_SPM_USING_SRCLKEN_RC
  119. ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
  120. #else
  121. allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
  122. #endif
  123. }
  124. #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
  125. mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
  126. (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
  127. #else
  128. (void)allows;
  129. #endif
  130. if (IS_PLAT_SUSPEND_ID(state_id)) {
  131. mt_spm_suspend_enter(state_id,
  132. (MT_SPM_EX_OP_SET_WDT |
  133. MT_SPM_EX_OP_HW_S1_DETECT |
  134. MT_SPM_EX_OP_SET_SUSPEND_MODE),
  135. CONSTRAINT_SYSPLL_RESOURCE_REQ);
  136. } else {
  137. mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
  138. }
  139. return 0;
  140. }
  141. int spm_reset_rc_syspll(unsigned int cpu, int state_id)
  142. {
  143. unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
  144. unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
  145. (void)cpu;
  146. if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
  147. #ifdef MT_SPM_USING_SRCLKEN_RC
  148. ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
  149. #else
  150. allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
  151. #endif
  152. }
  153. #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
  154. mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
  155. #else
  156. (void)allows;
  157. #endif
  158. if (IS_PLAT_SUSPEND_ID(state_id)) {
  159. mt_spm_suspend_resume(state_id,
  160. (MT_SPM_EX_OP_SET_SUSPEND_MODE |
  161. MT_SPM_EX_OP_SET_WDT |
  162. MT_SPM_EX_OP_HW_S1_DETECT),
  163. NULL);
  164. } else {
  165. mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
  166. status.enter_cnt++;
  167. }
  168. return 0;
  169. }