mtk_dcm_utils.c 15 KB

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  1. /*
  2. * Copyright (c) 2020, MediaTek Inc. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <lib/mmio.h>
  7. #include <lib/utils_def.h>
  8. #include <mtk_dcm_utils.h>
  9. #define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(17))
  10. #define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | \
  11. BIT(16) | \
  12. BIT(17) | \
  13. BIT(18) | \
  14. BIT(21))
  15. #define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | \
  16. BIT(16) | \
  17. BIT(17) | \
  18. BIT(18))
  19. #define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(17))
  20. #define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | \
  21. BIT(16) | \
  22. BIT(17) | \
  23. BIT(18) | \
  24. BIT(21))
  25. #define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | \
  26. BIT(16) | \
  27. BIT(17) | \
  28. BIT(18))
  29. #define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 17))
  30. #define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | \
  31. (0x0 << 16) | \
  32. (0x0 << 17) | \
  33. (0x0 << 18) | \
  34. (0x0 << 21))
  35. #define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | \
  36. (0x0 << 16) | \
  37. (0x0 << 17) | \
  38. (0x0 << 18))
  39. bool dcm_mp_cpusys_top_adb_dcm_is_on(void)
  40. {
  41. bool ret = true;
  42. ret &= ((mmio_read_32(MP_ADB_DCM_CFG0) &
  43. MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) ==
  44. (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
  45. ret &= ((mmio_read_32(MP_ADB_DCM_CFG4) &
  46. MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) ==
  47. (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
  48. ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) &
  49. MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) ==
  50. (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
  51. return ret;
  52. }
  53. void dcm_mp_cpusys_top_adb_dcm(bool on)
  54. {
  55. if (on) {
  56. /* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */
  57. mmio_clrsetbits_32(MP_ADB_DCM_CFG0,
  58. MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
  59. MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
  60. mmio_clrsetbits_32(MP_ADB_DCM_CFG4,
  61. MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
  62. MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
  63. mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
  64. MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
  65. MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
  66. } else {
  67. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */
  68. mmio_clrsetbits_32(MP_ADB_DCM_CFG0,
  69. MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
  70. MP_CPUSYS_TOP_ADB_DCM_REG0_OFF);
  71. mmio_clrsetbits_32(MP_ADB_DCM_CFG4,
  72. MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
  73. MP_CPUSYS_TOP_ADB_DCM_REG1_OFF);
  74. mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
  75. MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
  76. MP_CPUSYS_TOP_ADB_DCM_REG2_OFF);
  77. }
  78. }
  79. #define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5))
  80. #define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8))
  81. #define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16))
  82. #define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5))
  83. #define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8))
  84. #define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16))
  85. #define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5))
  86. #define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8))
  87. #define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16))
  88. bool dcm_mp_cpusys_top_apb_dcm_is_on(void)
  89. {
  90. bool ret = true;
  91. ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
  92. MP_CPUSYS_TOP_APB_DCM_REG0_MASK) ==
  93. (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON);
  94. ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) &
  95. MP_CPUSYS_TOP_APB_DCM_REG1_MASK) ==
  96. (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON);
  97. ret &= ((mmio_read_32(MP0_DCM_CFG0) &
  98. MP_CPUSYS_TOP_APB_DCM_REG2_MASK) ==
  99. (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON);
  100. return ret;
  101. }
  102. void dcm_mp_cpusys_top_apb_dcm(bool on)
  103. {
  104. if (on) {
  105. /* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */
  106. mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
  107. MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
  108. MP_CPUSYS_TOP_APB_DCM_REG0_ON);
  109. mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
  110. MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
  111. MP_CPUSYS_TOP_APB_DCM_REG1_ON);
  112. mmio_clrsetbits_32(MP0_DCM_CFG0,
  113. MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
  114. MP_CPUSYS_TOP_APB_DCM_REG2_ON);
  115. } else {
  116. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */
  117. mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
  118. MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
  119. MP_CPUSYS_TOP_APB_DCM_REG0_OFF);
  120. mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
  121. MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
  122. MP_CPUSYS_TOP_APB_DCM_REG1_OFF);
  123. mmio_clrsetbits_32(MP0_DCM_CFG0,
  124. MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
  125. MP_CPUSYS_TOP_APB_DCM_REG2_OFF);
  126. }
  127. }
  128. #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11))
  129. #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11))
  130. #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11))
  131. bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void)
  132. {
  133. bool ret = true;
  134. ret &= ((mmio_read_32(BUS_PLLDIV_CFG) &
  135. MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) ==
  136. (unsigned int) MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
  137. return ret;
  138. }
  139. void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on)
  140. {
  141. if (on) {
  142. /* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
  143. mmio_clrsetbits_32(BUS_PLLDIV_CFG,
  144. MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
  145. MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
  146. } else {
  147. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
  148. mmio_clrsetbits_32(BUS_PLLDIV_CFG,
  149. MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
  150. MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF);
  151. }
  152. }
  153. #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0))
  154. #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0))
  155. #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0))
  156. bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void)
  157. {
  158. bool ret = true;
  159. ret &= ((mmio_read_32(MP0_DCM_CFG7) &
  160. MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) ==
  161. (unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
  162. return ret;
  163. }
  164. void dcm_mp_cpusys_top_core_stall_dcm(bool on)
  165. {
  166. if (on) {
  167. /* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */
  168. mmio_clrsetbits_32(MP0_DCM_CFG7,
  169. MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
  170. MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
  171. } else {
  172. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */
  173. mmio_clrsetbits_32(MP0_DCM_CFG7,
  174. MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
  175. MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF);
  176. }
  177. }
  178. #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0))
  179. #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0))
  180. #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0))
  181. bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void)
  182. {
  183. bool ret = true;
  184. ret &= ((mmio_read_32(MCSI_DCM0) &
  185. MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) ==
  186. (unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
  187. return ret;
  188. }
  189. void dcm_mp_cpusys_top_cpubiu_dcm(bool on)
  190. {
  191. if (on) {
  192. /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */
  193. mmio_clrsetbits_32(MCSI_DCM0,
  194. MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
  195. MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
  196. } else {
  197. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */
  198. mmio_clrsetbits_32(MCSI_DCM0,
  199. MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
  200. MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF);
  201. }
  202. }
  203. #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(11))
  204. #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(11))
  205. #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 11))
  206. bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void)
  207. {
  208. bool ret = true;
  209. ret &= ((mmio_read_32(CPU_PLLDIV_CFG0) &
  210. MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) ==
  211. (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
  212. return ret;
  213. }
  214. void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on)
  215. {
  216. if (on) {
  217. /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
  218. mmio_clrsetbits_32(CPU_PLLDIV_CFG0,
  219. MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
  220. MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
  221. } else {
  222. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
  223. mmio_clrsetbits_32(CPU_PLLDIV_CFG0,
  224. MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
  225. MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF);
  226. }
  227. }
  228. #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(11))
  229. #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(11))
  230. #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 11))
  231. bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void)
  232. {
  233. bool ret = true;
  234. ret &= ((mmio_read_32(CPU_PLLDIV_CFG1) &
  235. MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) ==
  236. (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
  237. return ret;
  238. }
  239. void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on)
  240. {
  241. if (on) {
  242. /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
  243. mmio_clrsetbits_32(CPU_PLLDIV_CFG1,
  244. MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
  245. MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
  246. } else {
  247. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
  248. mmio_clrsetbits_32(CPU_PLLDIV_CFG1,
  249. MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
  250. MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF);
  251. }
  252. }
  253. #define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK (BIT(11))
  254. #define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON (BIT(11))
  255. #define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF ((0x0 << 11))
  256. bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void)
  257. {
  258. bool ret = true;
  259. ret &= ((mmio_read_32(CPU_PLLDIV_CFG2) &
  260. MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK) ==
  261. (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON);
  262. return ret;
  263. }
  264. void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(bool on)
  265. {
  266. if (on) {
  267. /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */
  268. mmio_clrsetbits_32(CPU_PLLDIV_CFG2,
  269. MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK,
  270. MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON);
  271. } else {
  272. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */
  273. mmio_clrsetbits_32(CPU_PLLDIV_CFG2,
  274. MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK,
  275. MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF);
  276. }
  277. }
  278. #define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK (BIT(11))
  279. #define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON (BIT(11))
  280. #define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF ((0x0 << 11))
  281. bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void)
  282. {
  283. bool ret = true;
  284. ret &= ((mmio_read_32(CPU_PLLDIV_CFG3) &
  285. MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK) ==
  286. (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON);
  287. return ret;
  288. }
  289. void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(bool on)
  290. {
  291. if (on) {
  292. /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */
  293. mmio_clrsetbits_32(CPU_PLLDIV_CFG3,
  294. MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK,
  295. MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON);
  296. } else {
  297. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */
  298. mmio_clrsetbits_32(CPU_PLLDIV_CFG3,
  299. MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK,
  300. MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF);
  301. }
  302. }
  303. #define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK (BIT(11))
  304. #define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON (BIT(11))
  305. #define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF ((0x0 << 11))
  306. bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void)
  307. {
  308. bool ret = true;
  309. ret &= ((mmio_read_32(CPU_PLLDIV_CFG4) &
  310. MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK) ==
  311. (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON);
  312. return ret;
  313. }
  314. void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(bool on)
  315. {
  316. if (on) {
  317. /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */
  318. mmio_clrsetbits_32(CPU_PLLDIV_CFG4,
  319. MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK,
  320. MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON);
  321. } else {
  322. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */
  323. mmio_clrsetbits_32(CPU_PLLDIV_CFG4,
  324. MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK,
  325. MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF);
  326. }
  327. }
  328. #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4))
  329. #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4))
  330. #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4))
  331. bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void)
  332. {
  333. bool ret = true;
  334. ret &= ((mmio_read_32(MP0_DCM_CFG7) &
  335. MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) ==
  336. (unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
  337. return ret;
  338. }
  339. void dcm_mp_cpusys_top_fcm_stall_dcm(bool on)
  340. {
  341. if (on) {
  342. /* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */
  343. mmio_clrsetbits_32(MP0_DCM_CFG7,
  344. MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
  345. MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
  346. } else {
  347. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */
  348. mmio_clrsetbits_32(MP0_DCM_CFG7,
  349. MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
  350. MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF);
  351. }
  352. }
  353. #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK ((0x1U << 31))
  354. #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON ((0x1U << 31))
  355. #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0U << 31))
  356. bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void)
  357. {
  358. bool ret = true;
  359. ret &= ((mmio_read_32(BUS_PLLDIV_CFG) &
  360. MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) ==
  361. (unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
  362. return ret;
  363. }
  364. void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on)
  365. {
  366. if (on) {
  367. /* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
  368. mmio_clrsetbits_32(BUS_PLLDIV_CFG,
  369. MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
  370. MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
  371. } else {
  372. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
  373. mmio_clrsetbits_32(BUS_PLLDIV_CFG,
  374. MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
  375. MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF);
  376. }
  377. }
  378. #define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | \
  379. BIT(4))
  380. #define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | \
  381. BIT(4))
  382. #define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | \
  383. (0x0 << 4))
  384. bool dcm_mp_cpusys_top_misc_dcm_is_on(void)
  385. {
  386. bool ret = true;
  387. ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
  388. MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) ==
  389. (unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
  390. return ret;
  391. }
  392. void dcm_mp_cpusys_top_misc_dcm(bool on)
  393. {
  394. if (on) {
  395. /* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */
  396. mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
  397. MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
  398. MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
  399. } else {
  400. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */
  401. mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
  402. MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
  403. MP_CPUSYS_TOP_MISC_DCM_REG0_OFF);
  404. }
  405. }
  406. #define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(3))
  407. #define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | \
  408. BIT(1) | \
  409. BIT(2) | \
  410. BIT(3))
  411. #define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(3))
  412. #define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | \
  413. BIT(1) | \
  414. BIT(2) | \
  415. BIT(3))
  416. #define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3))
  417. #define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | \
  418. (0x0 << 1) | \
  419. (0x0 << 2) | \
  420. (0x0 << 3))
  421. bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void)
  422. {
  423. bool ret = true;
  424. ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
  425. MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) ==
  426. (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
  427. ret &= ((mmio_read_32(MP0_DCM_CFG0) &
  428. MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) ==
  429. (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
  430. return ret;
  431. }
  432. void dcm_mp_cpusys_top_mp0_qdcm(bool on)
  433. {
  434. if (on) {
  435. /* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */
  436. mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
  437. MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
  438. MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
  439. mmio_clrsetbits_32(MP0_DCM_CFG0,
  440. MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
  441. MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
  442. } else {
  443. /* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */
  444. mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
  445. MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
  446. MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF);
  447. mmio_clrsetbits_32(MP0_DCM_CFG0,
  448. MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
  449. MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF);
  450. }
  451. }
  452. #define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | \
  453. BIT(1) | \
  454. BIT(2) | \
  455. BIT(3))
  456. #define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | \
  457. BIT(1) | \
  458. BIT(2) | \
  459. BIT(3))
  460. #define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | \
  461. (0x0 << 1) | \
  462. (0x0 << 2) | \
  463. (0x0 << 3))
  464. bool dcm_cpccfg_reg_emi_wfifo_is_on(void)
  465. {
  466. bool ret = true;
  467. ret &= ((mmio_read_32(EMI_WFIFO) &
  468. CPCCFG_REG_EMI_WFIFO_REG0_MASK) ==
  469. (unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON);
  470. return ret;
  471. }
  472. void dcm_cpccfg_reg_emi_wfifo(bool on)
  473. {
  474. if (on) {
  475. /* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */
  476. mmio_clrsetbits_32(EMI_WFIFO,
  477. CPCCFG_REG_EMI_WFIFO_REG0_MASK,
  478. CPCCFG_REG_EMI_WFIFO_REG0_ON);
  479. } else {
  480. /* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */
  481. mmio_clrsetbits_32(EMI_WFIFO,
  482. CPCCFG_REG_EMI_WFIFO_REG0_MASK,
  483. CPCCFG_REG_EMI_WFIFO_REG0_OFF);
  484. }
  485. }