pm_client.c 8.3 KB

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  1. /*
  2. * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
  3. * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-3-Clause
  6. */
  7. /*
  8. * APU specific definition of processors in the subsystem as well as functions
  9. * for getting information about and changing state of the APU.
  10. */
  11. #include <assert.h>
  12. #include <drivers/arm/gic_common.h>
  13. #include <drivers/arm/gicv3.h>
  14. #include <lib/bakery_lock.h>
  15. #include <lib/mmio.h>
  16. #include <lib/spinlock.h>
  17. #include <lib/utils.h>
  18. #include <plat/common/platform.h>
  19. #include <plat_ipi.h>
  20. #include <platform_def.h>
  21. #include "pm_api_sys.h"
  22. #include "pm_client.h"
  23. #include <versal_net_def.h>
  24. #define UNDEFINED_CPUID (~0)
  25. DEFINE_RENAME_SYSREG_RW_FUNCS(cpu_pwrctrl_val, S3_0_C15_C2_7)
  26. /*
  27. * ARM v8.2, the cache will turn off automatically when cpu
  28. * power down. Therefore, there is no doubt to use the spin_lock here.
  29. */
  30. #if !HW_ASSISTED_COHERENCY
  31. DEFINE_BAKERY_LOCK(pm_client_secure_lock);
  32. static inline void pm_client_lock_get(void)
  33. {
  34. bakery_lock_get(&pm_client_secure_lock);
  35. }
  36. static inline void pm_client_lock_release(void)
  37. {
  38. bakery_lock_release(&pm_client_secure_lock);
  39. }
  40. #else
  41. spinlock_t pm_client_secure_lock;
  42. static inline void pm_client_lock_get(void)
  43. {
  44. spin_lock(&pm_client_secure_lock);
  45. }
  46. static inline void pm_client_lock_release(void)
  47. {
  48. spin_unlock(&pm_client_secure_lock);
  49. }
  50. #endif
  51. static const struct pm_ipi apu_ipi = {
  52. .local_ipi_id = IPI_LOCAL_ID,
  53. .remote_ipi_id = IPI_REMOTE_ID,
  54. .buffer_base = IPI_BUFFER_LOCAL_BASE,
  55. };
  56. /* Order in pm_procs_all array must match cpu ids */
  57. static const struct pm_proc pm_procs_all[] = {
  58. {
  59. .node_id = PM_DEV_CLUSTER0_ACPU_0,
  60. .ipi = &apu_ipi,
  61. .pwrdn_mask = 0,
  62. },
  63. {
  64. .node_id = PM_DEV_CLUSTER0_ACPU_1,
  65. .ipi = &apu_ipi,
  66. .pwrdn_mask = 0,
  67. },
  68. {
  69. .node_id = PM_DEV_CLUSTER0_ACPU_2,
  70. .ipi = &apu_ipi,
  71. .pwrdn_mask = 0,
  72. },
  73. {
  74. .node_id = PM_DEV_CLUSTER0_ACPU_3,
  75. .ipi = &apu_ipi,
  76. .pwrdn_mask = 0,
  77. },
  78. {
  79. .node_id = PM_DEV_CLUSTER1_ACPU_0,
  80. .ipi = &apu_ipi,
  81. .pwrdn_mask = 0,
  82. },
  83. {
  84. .node_id = PM_DEV_CLUSTER1_ACPU_1,
  85. .ipi = &apu_ipi,
  86. .pwrdn_mask = 0,
  87. },
  88. {
  89. .node_id = PM_DEV_CLUSTER1_ACPU_2,
  90. .ipi = &apu_ipi,
  91. .pwrdn_mask = 0,
  92. },
  93. {
  94. .node_id = PM_DEV_CLUSTER1_ACPU_3,
  95. .ipi = &apu_ipi,
  96. .pwrdn_mask = 0,
  97. },
  98. {
  99. .node_id = PM_DEV_CLUSTER2_ACPU_0,
  100. .ipi = &apu_ipi,
  101. .pwrdn_mask = 0,
  102. },
  103. {
  104. .node_id = PM_DEV_CLUSTER2_ACPU_1,
  105. .ipi = &apu_ipi,
  106. .pwrdn_mask = 0,
  107. },
  108. {
  109. .node_id = PM_DEV_CLUSTER2_ACPU_2,
  110. .ipi = &apu_ipi,
  111. .pwrdn_mask = 0,
  112. },
  113. {
  114. .node_id = PM_DEV_CLUSTER2_ACPU_3,
  115. .ipi = &apu_ipi,
  116. .pwrdn_mask = 0,
  117. },
  118. {
  119. .node_id = PM_DEV_CLUSTER3_ACPU_0,
  120. .ipi = &apu_ipi,
  121. .pwrdn_mask = 0,
  122. },
  123. {
  124. .node_id = PM_DEV_CLUSTER3_ACPU_1,
  125. .ipi = &apu_ipi,
  126. .pwrdn_mask = 0,
  127. },
  128. {
  129. .node_id = PM_DEV_CLUSTER3_ACPU_2,
  130. .ipi = &apu_ipi,
  131. .pwrdn_mask = 0,
  132. },
  133. {
  134. .node_id = PM_DEV_CLUSTER3_ACPU_3,
  135. .ipi = &apu_ipi,
  136. .pwrdn_mask = 0,
  137. }
  138. };
  139. const struct pm_proc *primary_proc = &pm_procs_all[0];
  140. /**
  141. * pm_get_proc() - returns pointer to the proc structure.
  142. * @cpuid: id of the cpu whose proc struct pointer should be returned.
  143. *
  144. * Return: Pointer to a proc structure if proc is found, otherwise NULL.
  145. *
  146. */
  147. const struct pm_proc *pm_get_proc(uint32_t cpuid)
  148. {
  149. if (cpuid < ARRAY_SIZE(pm_procs_all)) {
  150. return &pm_procs_all[cpuid];
  151. }
  152. NOTICE("ERROR: cpuid: %d proc NULL\n", cpuid);
  153. return NULL;
  154. }
  155. /**
  156. * irq_to_pm_node_idx - Get PM node index corresponding to the interrupt number.
  157. * @irq: Interrupt number.
  158. *
  159. * Return: PM node index corresponding to the specified interrupt.
  160. *
  161. */
  162. enum pm_device_node_idx irq_to_pm_node_idx(uint32_t irq)
  163. {
  164. enum pm_device_node_idx dev_idx = XPM_NODEIDX_DEV_MIN;
  165. assert(irq <= IRQ_MAX);
  166. switch (irq) {
  167. case 20:
  168. dev_idx = XPM_NODEIDX_DEV_GPIO;
  169. break;
  170. case 21:
  171. dev_idx = XPM_NODEIDX_DEV_I2C_0;
  172. break;
  173. case 22:
  174. dev_idx = XPM_NODEIDX_DEV_I2C_1;
  175. break;
  176. case 23:
  177. dev_idx = XPM_NODEIDX_DEV_SPI_0;
  178. break;
  179. case 24:
  180. dev_idx = XPM_NODEIDX_DEV_SPI_1;
  181. break;
  182. case 25:
  183. dev_idx = XPM_NODEIDX_DEV_UART_0;
  184. break;
  185. case 26:
  186. dev_idx = XPM_NODEIDX_DEV_UART_1;
  187. break;
  188. case 27:
  189. dev_idx = XPM_NODEIDX_DEV_CAN_FD_0;
  190. break;
  191. case 28:
  192. dev_idx = XPM_NODEIDX_DEV_CAN_FD_1;
  193. break;
  194. case 29:
  195. case 30:
  196. case 31:
  197. case 32:
  198. case 33:
  199. case 98:
  200. dev_idx = XPM_NODEIDX_DEV_USB_0;
  201. break;
  202. case 34:
  203. case 35:
  204. case 36:
  205. case 37:
  206. case 38:
  207. case 99:
  208. dev_idx = XPM_NODEIDX_DEV_USB_1;
  209. break;
  210. case 39:
  211. case 40:
  212. dev_idx = XPM_NODEIDX_DEV_GEM_0;
  213. break;
  214. case 41:
  215. case 42:
  216. dev_idx = XPM_NODEIDX_DEV_GEM_1;
  217. break;
  218. case 43:
  219. case 44:
  220. case 45:
  221. dev_idx = XPM_NODEIDX_DEV_TTC_0;
  222. break;
  223. case 46:
  224. case 47:
  225. case 48:
  226. dev_idx = XPM_NODEIDX_DEV_TTC_1;
  227. break;
  228. case 49:
  229. case 50:
  230. case 51:
  231. dev_idx = XPM_NODEIDX_DEV_TTC_2;
  232. break;
  233. case 52:
  234. case 53:
  235. case 54:
  236. dev_idx = XPM_NODEIDX_DEV_TTC_3;
  237. break;
  238. case 72:
  239. dev_idx = XPM_NODEIDX_DEV_ADMA_0;
  240. break;
  241. case 73:
  242. dev_idx = XPM_NODEIDX_DEV_ADMA_1;
  243. break;
  244. case 74:
  245. dev_idx = XPM_NODEIDX_DEV_ADMA_2;
  246. break;
  247. case 75:
  248. dev_idx = XPM_NODEIDX_DEV_ADMA_3;
  249. break;
  250. case 76:
  251. dev_idx = XPM_NODEIDX_DEV_ADMA_4;
  252. break;
  253. case 77:
  254. dev_idx = XPM_NODEIDX_DEV_ADMA_5;
  255. break;
  256. case 78:
  257. dev_idx = XPM_NODEIDX_DEV_ADMA_6;
  258. break;
  259. case 79:
  260. dev_idx = XPM_NODEIDX_DEV_ADMA_7;
  261. break;
  262. case 184:
  263. case 185:
  264. dev_idx = XPM_NODEIDX_DEV_SDIO_0;
  265. break;
  266. case 186:
  267. case 187:
  268. dev_idx = XPM_NODEIDX_DEV_SDIO_1;
  269. break;
  270. case 200:
  271. dev_idx = XPM_NODEIDX_DEV_RTC;
  272. break;
  273. default:
  274. dev_idx = XPM_NODEIDX_DEV_MIN;
  275. break;
  276. }
  277. return dev_idx;
  278. }
  279. /**
  280. * pm_client_suspend() - Client-specific suspend actions. This function
  281. * should contain any PU-specific actions required
  282. * prior to sending suspend request to PMU. Actions
  283. * taken depend on the state system is suspending to.
  284. * @proc: processor which need to suspend.
  285. * @state: desired suspend state.
  286. *
  287. */
  288. void pm_client_suspend(const struct pm_proc *proc, uint32_t state)
  289. {
  290. uint32_t cpu_id = plat_my_core_pos();
  291. uintptr_t val;
  292. pm_client_lock_get();
  293. if (state == PM_STATE_SUSPEND_TO_RAM) {
  294. pm_client_set_wakeup_sources((uint32_t)proc->node_id);
  295. }
  296. val = read_cpu_pwrctrl_val();
  297. val |= CORE_PWRDN_EN_BIT_MASK;
  298. write_cpu_pwrctrl_val(val);
  299. isb();
  300. /* Enable power down interrupt */
  301. mmio_write_32(APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id),
  302. APU_PCIL_CORE_X_IEN_POWER_MASK);
  303. /* Enable wake interrupt */
  304. mmio_write_32(APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id),
  305. APU_PCIL_CORE_X_IEN_WAKE_MASK);
  306. pm_client_lock_release();
  307. }
  308. /**
  309. * pm_get_cpuid() - get the local cpu ID for a global node ID.
  310. * @nid: node id of the processor.
  311. *
  312. * Return: the cpu ID (starting from 0) for the subsystem.
  313. *
  314. */
  315. static uint32_t pm_get_cpuid(uint32_t nid)
  316. {
  317. for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
  318. if (pm_procs_all[i].node_id == nid) {
  319. return i;
  320. }
  321. }
  322. return UNDEFINED_CPUID;
  323. }
  324. /**
  325. * pm_client_wakeup() - Client-specific wakeup actions.
  326. * @proc: Processor which need to wakeup.
  327. *
  328. * This function should contain any PU-specific actions
  329. * required for waking up another APU core.
  330. *
  331. */
  332. void pm_client_wakeup(const struct pm_proc *proc)
  333. {
  334. uint32_t cpuid = pm_get_cpuid(proc->node_id);
  335. uintptr_t val;
  336. if (cpuid == UNDEFINED_CPUID) {
  337. return;
  338. }
  339. pm_client_lock_get();
  340. /* Clear powerdown request */
  341. val = read_cpu_pwrctrl_val();
  342. val &= ~CORE_PWRDN_EN_BIT_MASK;
  343. write_cpu_pwrctrl_val(val);
  344. isb();
  345. /* Disabled power down interrupt */
  346. mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid),
  347. APU_PCIL_CORE_X_IDS_POWER_MASK);
  348. /* Disable wake interrupt */
  349. mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(cpuid),
  350. APU_PCIL_CORE_X_IDS_WAKE_MASK);
  351. pm_client_lock_release();
  352. }
  353. /**
  354. * pm_client_abort_suspend() - Client-specific abort-suspend actions.
  355. *
  356. * This function should contain any PU-specific actions
  357. * required for aborting a prior suspend request.
  358. *
  359. */
  360. void pm_client_abort_suspend(void)
  361. {
  362. uint32_t cpu_id = plat_my_core_pos();
  363. uintptr_t val;
  364. /* Enable interrupts at processor level (for current cpu) */
  365. gicv3_cpuif_enable(plat_my_core_pos());
  366. pm_client_lock_get();
  367. /* Clear powerdown request */
  368. val = read_cpu_pwrctrl_val();
  369. val &= ~CORE_PWRDN_EN_BIT_MASK;
  370. write_cpu_pwrctrl_val(val);
  371. isb();
  372. /* Disabled power down interrupt */
  373. mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id),
  374. APU_PCIL_CORE_X_IDS_POWER_MASK);
  375. pm_client_lock_release();
  376. }