cdns_combo_phy.c 2.0 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283
  1. /*
  2. * Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <assert.h>
  7. #include <errno.h>
  8. #include <stdbool.h>
  9. #include <string.h>
  10. #include <arch_helpers.h>
  11. #include <common/debug.h>
  12. #include <drivers/cadence/cdns_combo_phy.h>
  13. #include <drivers/cadence/cdns_sdmmc.h>
  14. #include <drivers/delay_timer.h>
  15. #include <lib/mmio.h>
  16. #include <lib/utils.h>
  17. int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value,
  18. uint32_t phy_reg_data, uint32_t phy_reg_data_value)
  19. {
  20. uint32_t data = 0U;
  21. uint32_t value = 0U;
  22. /* Get PHY register address, write HRS04*/
  23. value = mmio_read_32(phy_reg_addr);
  24. value &= ~PHY_REG_ADDR_MASK;
  25. value |= phy_reg_addr_value;
  26. mmio_write_32(phy_reg_addr, value);
  27. data = mmio_read_32(phy_reg_addr);
  28. if ((data & PHY_REG_ADDR_MASK) != phy_reg_addr_value) {
  29. ERROR("PHY_REG_ADDR is not set properly\n");
  30. return -ENXIO;
  31. }
  32. /* Get PHY register data, write HRS05 */
  33. value &= ~PHY_REG_DATA_MASK;
  34. value |= phy_reg_data_value;
  35. mmio_write_32(phy_reg_data, value);
  36. data = mmio_read_32(phy_reg_data);
  37. if (data != phy_reg_data_value) {
  38. ERROR("PHY_REG_DATA is not set properly\n");
  39. return -ENXIO;
  40. }
  41. return 0;
  42. }
  43. int cdns_sd_card_detect(void)
  44. {
  45. uint32_t value = 0;
  46. /* Card detection */
  47. do {
  48. value = mmio_read_32(SDMMC_CDN(SRS09));
  49. /* Wait for card insertion. SRS09.CI = 1 */
  50. } while ((value & (1 << SDMMC_CDN_CI)) == 0);
  51. if ((value & (1 << SDMMC_CDN_CI)) == 0) {
  52. ERROR("Card does not detect\n");
  53. return -ENXIO;
  54. }
  55. return 0;
  56. }
  57. int cdns_emmc_card_reset(void)
  58. {
  59. uint32_t _status = 0;
  60. /* Reset embedded card */
  61. mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status);
  62. mdelay(68680); /* ~68680us */
  63. mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (0 << SDMMC_CDN_BP));
  64. udelay(340); /* ~340us */
  65. /* Turn on supply voltage */
  66. /* BVS = 7, BP = 1, BP2 only in UHS2 mode */
  67. mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status);
  68. return 0;
  69. }