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drivers
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marvell
/
comphy
/
phy-default-porting-layer.h

phy-default-porting-layer.h 1.9 KB
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  1. /*
    2. 

  2.  * Copyright (C) 2018 Marvell International Ltd.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier:     BSD-3-Clause
    5. 

  5.  * https://spdx.org/licenses
    6. 

  6.  */
    7. 

  7. 

  8. #ifndef PHY_DEFAULT_PORTING_LAYER_H
    9. 

  9. #define PHY_DEFAULT_PORTING_LAYER_H
    10. 

  10. 

  11. 

  12. #define MAX_LANE_NR		6
    13. 

  13. 

  14. #warning "Using default comphy params - you may need to suit them to your board"
    15. 

  15. 

  16. static const struct xfi_params
    17. 

  17. 	xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
    18. 

  18. 	[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
    19. 

  19. 		.g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x5f,
    20. 

  20. 		.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
    21. 

  21. 		.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x1,
    22. 

  22. 		.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
    23. 

  23. 		.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, .valid = 1
    24. 

  24. 	}
    25. 

  25. };
    26. 

  26. 

  27. static const struct sata_params
    28. 

  28. 	sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
    29. 

  29. 	[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
    30. 

  30. 		.g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
    31. 

  31. 		.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
    32. 

  32. 		.g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1,
    33. 

  33. 		.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
    34. 

  34. 		.g3_tx_amp_adj = 0x1,
    35. 

  35. 		.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
    36. 

  36. 		.g3_tx_emph_en = 0x0,
    37. 

  37. 		.g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1,
    38. 

  38. 		.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf,
    39. 

  39. 		.align90 = 0x61,
    40. 

  40. 		.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
    41. 

  41. 		.g3_rx_selmuff = 0x3,
    42. 

  42. 		.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
    43. 

  43. 		.g3_rx_selmufi = 0x3,
    44. 

  44. 		.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
    45. 

  45. 		.g3_rx_selmupf = 0x2,
    46. 

  46. 		.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
    47. 

  47. 		.g3_rx_selmupi = 0x2,
    48. 

  48. 		.polarity_invert = COMPHY_POLARITY_NO_INVERT,
    49. 

  49. 		.valid = 0x1
    50. 

  50. 	},
    51. 

  51. };
    52. 

  52. 

  53. static const struct usb_params
    54. 

  54. 	usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
    55. 

  55. 	[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
    56. 

  56. 		.polarity_invert = COMPHY_POLARITY_NO_INVERT
    57. 

  57. 	},
    58. 

  58. };
    59. 

  59. #endif /* PHY_DEFAULT_PORTING_LAYER_H */
    60.