arch_helpers.S 3.1 KB

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  1. /*
  2. * Copyright (c) 2022, Mediatek Inc. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <arch.h>
  7. #include <asm_macros.S>
  8. #include <assert_macros.S>
  9. #include <cpu_macros.S>
  10. #if CONFIG_MTK_MCUSYS
  11. #include <mcucfg.h>
  12. #endif
  13. #include <platform_def.h>
  14. /*
  15. * Declare as weak function so that can be
  16. * overwritten by platform helpers
  17. */
  18. .weak platform_mem_init
  19. .weak plat_core_pos_by_mpidr
  20. .weak plat_my_core_pos
  21. .weak plat_mediatek_calc_core_pos
  22. .global plat_mpidr_by_core_pos
  23. .global plat_reset_handler
  24. /* -----------------------------------------------------
  25. * unsigned long plat_mpidr_by_core_pos(uint32_t cpuid)
  26. * This function calcuate mpidr by cpu pos if cpu
  27. * topology is linear.
  28. *
  29. * Clobbers: x0-x1
  30. * -----------------------------------------------------
  31. */
  32. func plat_mpidr_by_core_pos
  33. lsl x0, x0, #MPIDR_AFF1_SHIFT
  34. mrs x1, mpidr_el1
  35. and x1, x1, #MPIDR_MT_MASK
  36. orr x0, x0, x1
  37. ret
  38. endfunc plat_mpidr_by_core_pos
  39. /* -----------------------------------------------------
  40. * unsigned int plat_my_core_pos(void)
  41. * This function uses the plat_arm_calc_core_pos()
  42. * definition to get the index of the calling CPU.
  43. * -----------------------------------------------------
  44. */
  45. func plat_my_core_pos
  46. mrs x0, mpidr_el1
  47. b plat_mediatek_calc_core_pos
  48. endfunc plat_my_core_pos
  49. /* -----------------------------------------------------
  50. * int plat_mediatek_calc_core_pos(u_register_t mpidr);
  51. *
  52. * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and
  53. * AFF0 is thread id. There is only one cluster in ARMv8.2
  54. * and one thread in current implementation.
  55. *
  56. * With this function: CorePos = CoreID (AFF1)
  57. * we do it with x0 = (x0 >> 8) & 0xff
  58. * -----------------------------------------------------
  59. */
  60. func plat_mediatek_calc_core_pos
  61. b plat_core_pos_by_mpidr
  62. endfunc plat_mediatek_calc_core_pos
  63. /* ------------------------------------------------------
  64. * int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
  65. *
  66. * This function implements a part of the critical
  67. * interface between the psci generic layer and the
  68. * platform that allows the former to query the platform
  69. * to convert an MPIDR to a unique linear index.
  70. *
  71. * Clobbers: x0-x1
  72. * ------------------------------------------------------
  73. */
  74. func plat_core_pos_by_mpidr
  75. mov x1, #MPIDR_AFFLVL_MASK
  76. and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
  77. ret
  78. endfunc plat_core_pos_by_mpidr
  79. /* --------------------------------------------------------
  80. * void platform_mem_init (void);
  81. *
  82. * Any memory init, relocation to be done before the
  83. * platform boots. Called very early in the boot process.
  84. * --------------------------------------------------------
  85. */
  86. func platform_mem_init
  87. ret
  88. endfunc platform_mem_init
  89. func plat_reset_handler
  90. #if CONFIG_MTK_MCUSYS
  91. mov x10, x30
  92. bl plat_my_core_pos
  93. mov x30, x10
  94. mov w1, #0x1
  95. lsl w1, w1, w0
  96. ldr x0, =CPC_MCUSYS_CPU_ON_SW_HINT_SET
  97. str w1, [x0]
  98. dsb sy
  99. #endif
  100. #if CONFIG_MTK_ECC
  101. mov x10, x30
  102. /* enable sequence of ecc for cpus */
  103. bl disable_core_ecc
  104. bl ft_ecc_clear_per_core
  105. bl enable_core_ecc
  106. mov x30, x10
  107. #endif
  108. ret
  109. endfunc plat_reset_handler