plat_memctrl.c 31 KB

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  1. /*
  2. * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  3. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-3-Clause
  6. */
  7. #include <assert.h>
  8. #include <common/bl_common.h>
  9. #include <mce.h>
  10. #include <memctrl_v2.h>
  11. #include <tegra186_private.h>
  12. #include <tegra_mc_def.h>
  13. #include <tegra_platform.h>
  14. #include <tegra_private.h>
  15. extern uint64_t tegra_bl31_phys_base;
  16. /*******************************************************************************
  17. * Array to hold stream_id override config register offsets
  18. ******************************************************************************/
  19. static const uint32_t tegra186_streamid_override_regs[] = {
  20. MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
  21. MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
  22. MC_STREAMID_OVERRIDE_CFG_SDMMCR,
  23. MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
  24. MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
  25. MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
  26. MC_STREAMID_OVERRIDE_CFG_SDMMCW,
  27. MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
  28. };
  29. /*******************************************************************************
  30. * Array to hold the security configs for stream IDs
  31. ******************************************************************************/
  32. static const mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
  33. mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
  34. mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, DISABLE),
  35. mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, DISABLE),
  36. mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE),
  37. mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
  38. mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
  39. mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
  40. mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
  41. mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
  42. mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE),
  43. mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
  44. mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE),
  45. mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE),
  46. mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE),
  47. mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE),
  48. mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
  49. mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE),
  50. mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, DISABLE),
  51. mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE),
  52. mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, DISABLE),
  53. mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, DISABLE),
  54. mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE),
  55. mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE),
  56. mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
  57. mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
  58. mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
  59. mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE),
  60. mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
  61. mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE),
  62. mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
  63. mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
  64. mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, DISABLE),
  65. mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
  66. mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
  67. mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE),
  68. mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
  69. mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
  70. mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
  71. mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
  72. mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
  73. mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, DISABLE),
  74. mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE),
  75. mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
  76. mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
  77. mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
  78. mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
  79. mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
  80. mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE),
  81. mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE),
  82. mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
  83. mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
  84. mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
  85. mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE),
  86. mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE),
  87. mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
  88. mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE),
  89. mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE),
  90. mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE),
  91. mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE),
  92. mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE),
  93. mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE),
  94. mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE),
  95. mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE),
  96. mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
  97. mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE),
  98. mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
  99. mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
  100. mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
  101. mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
  102. mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE),
  103. mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE),
  104. mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
  105. };
  106. /*******************************************************************************
  107. * Array to hold the transaction override configs
  108. ******************************************************************************/
  109. static const mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = {
  110. mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
  111. mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
  112. mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
  113. mc_make_txn_override_cfg(SDMMCWAA, CGID_TAG_ADR),
  114. mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR),
  115. mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
  116. mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
  117. mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
  118. mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
  119. mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR),
  120. mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
  121. mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
  122. mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR),
  123. mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
  124. mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
  125. mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
  126. mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
  127. mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
  128. mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
  129. mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
  130. mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
  131. mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
  132. mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
  133. mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
  134. mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
  135. mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
  136. mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
  137. mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
  138. mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
  139. mc_make_txn_override_cfg(AFIW, CGID_TAG_ADR),
  140. mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
  141. };
  142. static void tegra186_memctrl_reconfig_mss_clients(void)
  143. {
  144. #if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS
  145. uint32_t val, wdata_0, wdata_1;
  146. /*
  147. * Assert Memory Controller's HOTRESET_FLUSH_ENABLE signal for
  148. * boot and strongly ordered MSS clients to flush existing memory
  149. * traffic and stall future requests.
  150. */
  151. val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
  152. assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
  153. wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
  154. MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
  155. MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
  156. MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
  157. MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB;
  158. tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
  159. /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
  160. do {
  161. val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
  162. } while ((val & wdata_0) != wdata_0);
  163. /* Wait one more time due to SW WAR for known legacy issue */
  164. do {
  165. val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
  166. } while ((val & wdata_0) != wdata_0);
  167. val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
  168. assert(val == MC_CLIENT_HOTRESET_CTRL1_RESET_VAL);
  169. wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
  170. MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
  171. MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
  172. MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
  173. MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
  174. MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
  175. MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
  176. MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
  177. MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
  178. MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB;
  179. tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
  180. /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
  181. do {
  182. val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
  183. } while ((val & wdata_1) != wdata_1);
  184. /* Wait one more time due to SW WAR for known legacy issue */
  185. do {
  186. val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
  187. } while ((val & wdata_1) != wdata_1);
  188. /*
  189. * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
  190. * strongly ordered MSS clients. ROC needs to be single point
  191. * of control on overriding the memory type. So, remove TSA's
  192. * memtype override.
  193. *
  194. * MC clients with default SO_DEV override still enabled at TSA:
  195. * AONW, BPMPW, SCEW, APEW
  196. */
  197. mc_set_tsa_passthrough(AFIW);
  198. mc_set_tsa_passthrough(HDAW);
  199. mc_set_tsa_passthrough(SATAW);
  200. mc_set_tsa_passthrough(XUSB_HOSTW);
  201. mc_set_tsa_passthrough(XUSB_DEVW);
  202. mc_set_tsa_passthrough(SDMMCWAB);
  203. mc_set_tsa_passthrough(APEDMAW);
  204. mc_set_tsa_passthrough(SESWR);
  205. mc_set_tsa_passthrough(ETRW);
  206. mc_set_tsa_passthrough(AXISW);
  207. mc_set_tsa_passthrough(EQOSW);
  208. mc_set_tsa_passthrough(UFSHCW);
  209. mc_set_tsa_passthrough(BPMPDMAW);
  210. mc_set_tsa_passthrough(AONDMAW);
  211. mc_set_tsa_passthrough(SCEDMAW);
  212. /* Parker has no IO Coherency support and need the following:
  213. * Ordered MC Clients on Parker are AFI, EQOS, SATA, XUSB.
  214. * ISO clients(DISP, VI, EQOS) should never snoop caches and
  215. * don't need ROC/PCFIFO ordering.
  216. * ISO clients(EQOS) that need ordering should use PCFIFO ordering
  217. * and bypass ROC ordering by using FORCE_NON_COHERENT path.
  218. * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
  219. * over SMMU attributes.
  220. * Force all Normal memory transactions from ISO and non-ISO to be
  221. * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
  222. * Force the SO_DEV transactions from ordered ISO clients(EQOS) to
  223. * non-coherent path and enable MC PCFIFO interlock for ordering.
  224. * Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
  225. * XUSB, SATA) to coherent so that the transactions are
  226. * ordered by ROC.
  227. * PCFIFO ensure write ordering.
  228. * Read after Write ordering is maintained/enforced by MC clients.
  229. * Clients that need PCIe type write ordering must
  230. * go through ROC ordering.
  231. * Ordering enable for Read clients is not necessary.
  232. * R5's and A9 would get necessary ordering from AXI and
  233. * don't need ROC ordering enable:
  234. * - MMIO ordering is through dev mapping and MMIO
  235. * accesses bypass SMMU.
  236. * - Normal memory is accessed through SMMU and ordering is
  237. * ensured by client and AXI.
  238. * - Ack point for Normal memory is WCAM in MC.
  239. * - MMIO's can be early acked and AXI ensures dev memory ordering,
  240. * Client ensures read/write direction change ordering.
  241. * - See Bug 200312466 for more details.
  242. *
  243. * CGID_TAG_ADR is only present from T186 A02. As this code is common
  244. * between A01 and A02, tegra_memctrl_set_overrides() programs
  245. * CGID_TAG_ADR for the necessary clients on A02.
  246. */
  247. mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  248. mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  249. mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  250. mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  251. mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  252. mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  253. mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  254. mc_set_txn_override(SDMMCWAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  255. mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  256. mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
  257. mc_set_txn_override(GPUSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  258. mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  259. mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  260. mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  261. mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  262. /* See bug 200131110 comment #35*/
  263. mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  264. mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  265. mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  266. mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  267. mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  268. mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  269. mc_set_txn_override(SDMMCRAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  270. mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  271. mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  272. mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  273. mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  274. mc_set_txn_override(GPUSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  275. mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  276. mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
  277. mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  278. mc_set_txn_override(GPUSRD2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  279. mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  280. mc_set_txn_override(GPUSWR2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  281. mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  282. /* See bug 200131110 comment #35*/
  283. mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  284. mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  285. mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  286. mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  287. mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  288. mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  289. mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  290. mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  291. mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  292. mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  293. mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  294. mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  295. mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  296. mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  297. mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  298. mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  299. mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
  300. mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  301. mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  302. mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  303. mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  304. mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  305. mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
  306. mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  307. mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  308. mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  309. /* See bug 200131110 comment #35 */
  310. mc_set_txn_override(AFIR, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  311. mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  312. mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  313. mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  314. mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  315. mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  316. mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  317. mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  318. mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
  319. mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  320. /*
  321. * See bug 200131110 comment #35 - there are no normal requests
  322. * and AWID for SO/DEV requests is hardcoded in RTL for a
  323. * particular PCIE controller
  324. */
  325. mc_set_txn_override(AFIW, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_COHERENT);
  326. mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
  327. /*
  328. * At this point, ordering can occur at ROC. So, remove PCFIFO's
  329. * control over ordering requests.
  330. *
  331. * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
  332. * boot and strongly ordered MSS clients
  333. */
  334. val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
  335. mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) &
  336. mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) &
  337. mc_set_pcfifo_unordered_boot_so_mss(1, SATAW);
  338. tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
  339. val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
  340. mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
  341. mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_DEVW);
  342. tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val);
  343. val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
  344. mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB);
  345. tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val);
  346. val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
  347. mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
  348. mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
  349. mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
  350. mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
  351. mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
  352. mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
  353. mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
  354. /* EQOSW is the only client that has PCFIFO order enabled. */
  355. val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
  356. tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val);
  357. val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
  358. mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW);
  359. tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val);
  360. /*
  361. * Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS
  362. * clients to allow memory traffic from all clients to start passing
  363. * through ROC
  364. */
  365. val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
  366. assert(val == wdata_0);
  367. wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
  368. tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
  369. val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
  370. assert(val == wdata_1);
  371. wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
  372. tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
  373. #endif
  374. }
  375. static void tegra186_memctrl_set_overrides(void)
  376. {
  377. uint32_t i, val;
  378. /*
  379. * Set the MC_TXN_OVERRIDE registers for write clients.
  380. */
  381. if ((tegra_chipid_is_t186()) &&
  382. (!tegra_platform_is_silicon() ||
  383. (tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1U)))) {
  384. /*
  385. * GPU and NVENC settings for Tegra186 simulation and
  386. * Silicon rev. A01
  387. */
  388. val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
  389. val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
  390. tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
  391. val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
  392. val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
  393. val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
  394. tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
  395. val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
  396. val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
  397. val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
  398. tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
  399. val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
  400. } else {
  401. /*
  402. * Settings for Tegra186 silicon rev. A02 and onwards.
  403. */
  404. for (i = 0; i < ARRAY_SIZE(tegra186_txn_override_cfgs); i++) {
  405. val = tegra_mc_read_32(tegra186_txn_override_cfgs[i].offset);
  406. val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
  407. tegra_mc_write_32(tegra186_txn_override_cfgs[i].offset,
  408. val | tegra186_txn_override_cfgs[i].cgid_tag);
  409. }
  410. }
  411. }
  412. /*******************************************************************************
  413. * Array to hold MC context for Tegra186
  414. ******************************************************************************/
  415. static __attribute__((aligned(16))) mc_regs_t tegra186_mc_context[] = {
  416. _START_OF_TABLE_,
  417. mc_make_sid_security_cfg(SCEW),
  418. mc_make_sid_security_cfg(AFIR),
  419. mc_make_sid_security_cfg(NVDISPLAYR1),
  420. mc_make_sid_security_cfg(XUSB_DEVR),
  421. mc_make_sid_security_cfg(VICSRD1),
  422. mc_make_sid_security_cfg(NVENCSWR),
  423. mc_make_sid_security_cfg(TSECSRDB),
  424. mc_make_sid_security_cfg(AXISW),
  425. mc_make_sid_security_cfg(SDMMCWAB),
  426. mc_make_sid_security_cfg(AONDMAW),
  427. mc_make_sid_security_cfg(GPUSWR2),
  428. mc_make_sid_security_cfg(SATAW),
  429. mc_make_sid_security_cfg(UFSHCW),
  430. mc_make_sid_security_cfg(AFIW),
  431. mc_make_sid_security_cfg(SDMMCR),
  432. mc_make_sid_security_cfg(SCEDMAW),
  433. mc_make_sid_security_cfg(UFSHCR),
  434. mc_make_sid_security_cfg(SDMMCWAA),
  435. mc_make_sid_security_cfg(APEDMAW),
  436. mc_make_sid_security_cfg(SESWR),
  437. mc_make_sid_security_cfg(MPCORER),
  438. mc_make_sid_security_cfg(PTCR),
  439. mc_make_sid_security_cfg(BPMPW),
  440. mc_make_sid_security_cfg(ETRW),
  441. mc_make_sid_security_cfg(GPUSRD),
  442. mc_make_sid_security_cfg(VICSWR),
  443. mc_make_sid_security_cfg(SCEDMAR),
  444. mc_make_sid_security_cfg(HDAW),
  445. mc_make_sid_security_cfg(ISPWA),
  446. mc_make_sid_security_cfg(EQOSW),
  447. mc_make_sid_security_cfg(XUSB_HOSTW),
  448. mc_make_sid_security_cfg(TSECSWR),
  449. mc_make_sid_security_cfg(SDMMCRAA),
  450. mc_make_sid_security_cfg(APER),
  451. mc_make_sid_security_cfg(VIW),
  452. mc_make_sid_security_cfg(APEW),
  453. mc_make_sid_security_cfg(AXISR),
  454. mc_make_sid_security_cfg(SDMMCW),
  455. mc_make_sid_security_cfg(BPMPDMAW),
  456. mc_make_sid_security_cfg(ISPRA),
  457. mc_make_sid_security_cfg(NVDECSWR),
  458. mc_make_sid_security_cfg(XUSB_DEVW),
  459. mc_make_sid_security_cfg(NVDECSRD),
  460. mc_make_sid_security_cfg(MPCOREW),
  461. mc_make_sid_security_cfg(NVDISPLAYR),
  462. mc_make_sid_security_cfg(BPMPDMAR),
  463. mc_make_sid_security_cfg(NVJPGSWR),
  464. mc_make_sid_security_cfg(NVDECSRD1),
  465. mc_make_sid_security_cfg(TSECSRD),
  466. mc_make_sid_security_cfg(NVJPGSRD),
  467. mc_make_sid_security_cfg(SDMMCWA),
  468. mc_make_sid_security_cfg(SCER),
  469. mc_make_sid_security_cfg(XUSB_HOSTR),
  470. mc_make_sid_security_cfg(VICSRD),
  471. mc_make_sid_security_cfg(AONDMAR),
  472. mc_make_sid_security_cfg(AONW),
  473. mc_make_sid_security_cfg(SDMMCRA),
  474. mc_make_sid_security_cfg(HOST1XDMAR),
  475. mc_make_sid_security_cfg(EQOSR),
  476. mc_make_sid_security_cfg(SATAR),
  477. mc_make_sid_security_cfg(BPMPR),
  478. mc_make_sid_security_cfg(HDAR),
  479. mc_make_sid_security_cfg(SDMMCRAB),
  480. mc_make_sid_security_cfg(ETRR),
  481. mc_make_sid_security_cfg(AONR),
  482. mc_make_sid_security_cfg(APEDMAR),
  483. mc_make_sid_security_cfg(SESRD),
  484. mc_make_sid_security_cfg(NVENCSRD),
  485. mc_make_sid_security_cfg(GPUSWR),
  486. mc_make_sid_security_cfg(TSECSWRB),
  487. mc_make_sid_security_cfg(ISPWB),
  488. mc_make_sid_security_cfg(GPUSRD2),
  489. mc_make_sid_override_cfg(APER),
  490. mc_make_sid_override_cfg(VICSRD),
  491. mc_make_sid_override_cfg(NVENCSRD),
  492. mc_make_sid_override_cfg(NVJPGSWR),
  493. mc_make_sid_override_cfg(AONW),
  494. mc_make_sid_override_cfg(BPMPR),
  495. mc_make_sid_override_cfg(BPMPW),
  496. mc_make_sid_override_cfg(HDAW),
  497. mc_make_sid_override_cfg(NVDISPLAYR1),
  498. mc_make_sid_override_cfg(APEDMAR),
  499. mc_make_sid_override_cfg(AFIR),
  500. mc_make_sid_override_cfg(AXISR),
  501. mc_make_sid_override_cfg(VICSRD1),
  502. mc_make_sid_override_cfg(TSECSRD),
  503. mc_make_sid_override_cfg(BPMPDMAW),
  504. mc_make_sid_override_cfg(MPCOREW),
  505. mc_make_sid_override_cfg(XUSB_HOSTR),
  506. mc_make_sid_override_cfg(GPUSWR),
  507. mc_make_sid_override_cfg(XUSB_DEVR),
  508. mc_make_sid_override_cfg(UFSHCW),
  509. mc_make_sid_override_cfg(XUSB_HOSTW),
  510. mc_make_sid_override_cfg(SDMMCWAB),
  511. mc_make_sid_override_cfg(SATAW),
  512. mc_make_sid_override_cfg(SCEDMAR),
  513. mc_make_sid_override_cfg(HOST1XDMAR),
  514. mc_make_sid_override_cfg(SDMMCWA),
  515. mc_make_sid_override_cfg(APEDMAW),
  516. mc_make_sid_override_cfg(SESWR),
  517. mc_make_sid_override_cfg(AXISW),
  518. mc_make_sid_override_cfg(AONDMAW),
  519. mc_make_sid_override_cfg(TSECSWRB),
  520. mc_make_sid_override_cfg(MPCORER),
  521. mc_make_sid_override_cfg(ISPWB),
  522. mc_make_sid_override_cfg(AONR),
  523. mc_make_sid_override_cfg(BPMPDMAR),
  524. mc_make_sid_override_cfg(HDAR),
  525. mc_make_sid_override_cfg(SDMMCRA),
  526. mc_make_sid_override_cfg(ETRW),
  527. mc_make_sid_override_cfg(GPUSWR2),
  528. mc_make_sid_override_cfg(EQOSR),
  529. mc_make_sid_override_cfg(TSECSWR),
  530. mc_make_sid_override_cfg(ETRR),
  531. mc_make_sid_override_cfg(NVDECSRD),
  532. mc_make_sid_override_cfg(TSECSRDB),
  533. mc_make_sid_override_cfg(SDMMCRAA),
  534. mc_make_sid_override_cfg(NVDECSRD1),
  535. mc_make_sid_override_cfg(SDMMCR),
  536. mc_make_sid_override_cfg(NVJPGSRD),
  537. mc_make_sid_override_cfg(SCEDMAW),
  538. mc_make_sid_override_cfg(SDMMCWAA),
  539. mc_make_sid_override_cfg(APEW),
  540. mc_make_sid_override_cfg(AONDMAR),
  541. mc_make_sid_override_cfg(PTCR),
  542. mc_make_sid_override_cfg(SCER),
  543. mc_make_sid_override_cfg(ISPRA),
  544. mc_make_sid_override_cfg(ISPWA),
  545. mc_make_sid_override_cfg(VICSWR),
  546. mc_make_sid_override_cfg(SESRD),
  547. mc_make_sid_override_cfg(SDMMCW),
  548. mc_make_sid_override_cfg(SDMMCRAB),
  549. mc_make_sid_override_cfg(EQOSW),
  550. mc_make_sid_override_cfg(GPUSRD2),
  551. mc_make_sid_override_cfg(SCEW),
  552. mc_make_sid_override_cfg(GPUSRD),
  553. mc_make_sid_override_cfg(NVDECSWR),
  554. mc_make_sid_override_cfg(XUSB_DEVW),
  555. mc_make_sid_override_cfg(SATAR),
  556. mc_make_sid_override_cfg(NVDISPLAYR),
  557. mc_make_sid_override_cfg(VIW),
  558. mc_make_sid_override_cfg(UFSHCR),
  559. mc_make_sid_override_cfg(NVENCSWR),
  560. mc_make_sid_override_cfg(AFIW),
  561. mc_smmu_bypass_cfg, /* TBU settings */
  562. _END_OF_TABLE_,
  563. };
  564. /*******************************************************************************
  565. * Handler to return the pointer to the MC's context struct
  566. ******************************************************************************/
  567. mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void)
  568. {
  569. /* index of _END_OF_TABLE_ */
  570. tegra186_mc_context[0].val = (uint32_t)(ARRAY_SIZE(tegra186_mc_context)) - 1U;
  571. return tegra186_mc_context;
  572. }
  573. void plat_memctrl_setup(void)
  574. {
  575. uint32_t val;
  576. unsigned int i;
  577. /* Program all the Stream ID overrides */
  578. for (i = 0U; i < ARRAY_SIZE(tegra186_streamid_override_regs); i++) {
  579. tegra_mc_streamid_write_32(tegra186_streamid_override_regs[i],
  580. MC_STREAM_ID_MAX);
  581. }
  582. /* Program the security config settings for all Stream IDs */
  583. for (i = 0U; i < ARRAY_SIZE(tegra186_streamid_sec_cfgs); i++) {
  584. val = (tegra186_streamid_sec_cfgs[i].override_enable << 16) |
  585. (tegra186_streamid_sec_cfgs[i].override_client_inputs << 8) |
  586. (tegra186_streamid_sec_cfgs[i].override_client_ns_flag << 0);
  587. tegra_mc_streamid_write_32(tegra186_streamid_sec_cfgs[i].offset, val);
  588. }
  589. /*
  590. * Re-configure MSS to allow ROC to deal with ordering of the
  591. * Memory Controller traffic. This is needed as the Memory Controller
  592. * boots with MSS having all control, but ROC provides a performance
  593. * boost as compared to MSS.
  594. */
  595. tegra186_memctrl_reconfig_mss_clients();
  596. /* Program overrides for MC transactions */
  597. tegra186_memctrl_set_overrides();
  598. }
  599. /*******************************************************************************
  600. * Handler to restore platform specific settings to the memory controller
  601. ******************************************************************************/
  602. void plat_memctrl_restore(void)
  603. {
  604. /*
  605. * Re-configure MSS to allow ROC to deal with ordering of the
  606. * Memory Controller traffic. This is needed as the Memory Controller
  607. * boots with MSS having all control, but ROC provides a performance
  608. * boost as compared to MSS.
  609. */
  610. tegra186_memctrl_reconfig_mss_clients();
  611. /* Program overrides for MC transactions */
  612. tegra186_memctrl_set_overrides();
  613. }
  614. /*******************************************************************************
  615. * Handler to program the scratch registers with TZDRAM settings for the
  616. * resume firmware
  617. ******************************************************************************/
  618. void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
  619. {
  620. uint32_t val;
  621. /*
  622. * Setup the Memory controller to allow only secure accesses to
  623. * the TZDRAM carveout
  624. */
  625. INFO("Configuring TrustZone DRAM Memory Carveout\n");
  626. tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
  627. tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
  628. tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
  629. /*
  630. * When TZ encryption is enabled, we need to setup TZDRAM
  631. * before CPU accesses TZ Carveout, else CPU will fetch
  632. * non-decrypted data. So save TZDRAM setting for SC7 resume
  633. * FW to restore.
  634. *
  635. * Scratch registers map:
  636. * RSV55_0 = CFG1[12:0] | CFG0[31:20]
  637. * RSV55_1 = CFG3[1:0]
  638. */
  639. val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK;
  640. val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK;
  641. mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_LO, val);
  642. val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK;
  643. mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val);
  644. /*
  645. * MCE propagates the security configuration values across the
  646. * CCPLEX.
  647. */
  648. (void)mce_update_gsc_tzdram();
  649. }