Home Esplora Aiuto
Accedi
OWEALs
/
arm-trusted-firmware
mirror da https://github.com/ARM-software/arm-trusted-firmware
2
0
Forka 0
File Problemi 1 Wiki
Albero (Tree): 4ec2948fe3
Rami (Branch) Tag
arm-trusted-fir...
/
plat
/
rockchip
/
rk3399
/
include
/
shared
/
addressmap_shared.h

addressmap_shared.h 3.5 KB
Cronologia Originale

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104 
  1. /*
    2. 

  2.  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef ADDRESSMAP_SHARED_H
    8. 

  8. #define ADDRESSMAP_SHARED_H
    9. 

  9. 

  10. #define SIZE_K(n)		((n) * 1024)
    11. 

  11. #define SIZE_M(n)		((n) * 1024 * 1024)
    12. 

  12. #define SRAM_TEXT_LIMIT		(4 * 1024)
    13. 

  13. #define SRAM_DATA_LIMIT		(4 * 1024)
    14. 

  14. #define SRAM_BIN_LIMIT		(4 * 1024)
    15. 

  15. 

  16. /*
    17. 

  17.  * The parts of the shared defined registers address with AP and M0,
    18. 

  18.  * let's note and mark the previous defines like this:
    19. 

  19.  */
    20. 

  20. #define GIC500_BASE		(MMIO_BASE + 0x06E00000)
    21. 

  21. #define UART0_BASE		(MMIO_BASE + 0x07180000)
    22. 

  22. #define UART1_BASE		(MMIO_BASE + 0x07190000)
    23. 

  23. #define UART2_BASE		(MMIO_BASE + 0x071A0000)
    24. 

  24. #define UART3_BASE		(MMIO_BASE + 0x071B0000)
    25. 

  25. 

  26. #define PMU_BASE		(MMIO_BASE + 0x07310000)
    27. 

  27. #define PMUGRF_BASE		(MMIO_BASE + 0x07320000)
    28. 

  28. #define SGRF_BASE		(MMIO_BASE + 0x07330000)
    29. 

  29. #define PMUSRAM_BASE		(MMIO_BASE + 0x073B0000)
    30. 

  30. #define PWM_BASE		(MMIO_BASE + 0x07420000)
    31. 

  31. 

  32. #define CIC_BASE		(MMIO_BASE + 0x07620000)
    33. 

  33. #define PD_BUS0_BASE		(MMIO_BASE + 0x07650000)
    34. 

  34. #define DCF_BASE		(MMIO_BASE + 0x076A0000)
    35. 

  35. #define GPIO0_BASE		(MMIO_BASE + 0x07720000)
    36. 

  36. #define GPIO1_BASE		(MMIO_BASE + 0x07730000)
    37. 

  37. #define PMUCRU_BASE		(MMIO_BASE + 0x07750000)
    38. 

  38. #define CRU_BASE		(MMIO_BASE + 0x07760000)
    39. 

  39. #define GRF_BASE		(MMIO_BASE + 0x07770000)
    40. 

  40. #define GPIO2_BASE		(MMIO_BASE + 0x07780000)
    41. 

  41. #define GPIO3_BASE		(MMIO_BASE + 0x07788000)
    42. 

  42. #define GPIO4_BASE		(MMIO_BASE + 0x07790000)
    43. 

  43. #define WDT1_BASE		(MMIO_BASE + 0x07840000)
    44. 

  44. #define WDT0_BASE		(MMIO_BASE + 0x07848000)
    45. 

  45. #define TIMER_BASE		(MMIO_BASE + 0x07850000)
    46. 

  46. #define STIME_BASE		(MMIO_BASE + 0x07860000)
    47. 

  47. #define SRAM_BASE		(MMIO_BASE + 0x078C0000)
    48. 

  48. #define SERVICE_NOC_0_BASE	(MMIO_BASE + 0x07A50000)
    49. 

  49. #define DDRC0_BASE		(MMIO_BASE + 0x07A80000)
    50. 

  50. #define SERVICE_NOC_1_BASE	(MMIO_BASE + 0x07A84000)
    51. 

  51. #define DDRC1_BASE		(MMIO_BASE + 0x07A88000)
    52. 

  52. #define SERVICE_NOC_2_BASE	(MMIO_BASE + 0x07A8C000)
    53. 

  53. #define SERVICE_NOC_3_BASE	(MMIO_BASE + 0x07A90000)
    54. 

  54. #define CCI500_BASE		(MMIO_BASE + 0x07B00000)
    55. 

  55. #define COLD_BOOT_BASE		(MMIO_BASE + 0x07FF0000)
    56. 

  56. 

  57. /* Registers size */
    58. 

  58. #define GIC500_SIZE		SIZE_M(2)
    59. 

  59. #define UART0_SIZE		SIZE_K(64)
    60. 

  60. #define UART1_SIZE		SIZE_K(64)
    61. 

  61. #define UART2_SIZE		SIZE_K(64)
    62. 

  62. #define UART3_SIZE		SIZE_K(64)
    63. 

  63. #define PMU_SIZE		SIZE_K(64)
    64. 

  64. #define PMUGRF_SIZE		SIZE_K(64)
    65. 

  65. #define SGRF_SIZE		SIZE_K(64)
    66. 

  66. #define PMUSRAM_SIZE		SIZE_K(64)
    67. 

  67. #define PMUSRAM_RSIZE		SIZE_K(8)
    68. 

  68. #define PWM_SIZE		SIZE_K(64)
    69. 

  69. #define CIC_SIZE		SIZE_K(4)
    70. 

  70. #define DCF_SIZE		SIZE_K(4)
    71. 

  71. #define GPIO0_SIZE		SIZE_K(64)
    72. 

  72. #define GPIO1_SIZE		SIZE_K(64)
    73. 

  73. #define PMUCRU_SIZE		SIZE_K(64)
    74. 

  74. #define CRU_SIZE		SIZE_K(64)
    75. 

  75. #define GRF_SIZE		SIZE_K(64)
    76. 

  76. #define GPIO2_SIZE		SIZE_K(32)
    77. 

  77. #define GPIO3_SIZE		SIZE_K(32)
    78. 

  78. #define GPIO4_SIZE		SIZE_K(32)
    79. 

  79. #define STIME_SIZE		SIZE_K(64)
    80. 

  80. #define SRAM_SIZE		SIZE_K(192)
    81. 

  81. #define SERVICE_NOC_0_SIZE	SIZE_K(192)
    82. 

  82. #define DDRC0_SIZE		SIZE_K(32)
    83. 

  83. #define SERVICE_NOC_1_SIZE	SIZE_K(16)
    84. 

  84. #define DDRC1_SIZE		SIZE_K(32)
    85. 

  85. #define SERVICE_NOC_2_SIZE	SIZE_K(16)
    86. 

  86. #define SERVICE_NOC_3_SIZE	SIZE_K(448)
    87. 

  87. #define CCI500_SIZE		SIZE_M(1)
    88. 

  88. #define PD_BUS0_SIZE		SIZE_K(448)
    89. 

  89. 

  90. /* DDR Registers address */
    91. 

  91. #define CTL_BASE(ch)		(DDRC0_BASE + (ch) * 0x8000)
    92. 

  92. #define CTL_REG(ch, n)		(CTL_BASE(ch) + (n) * 0x4)
    93. 

  93. 

  94. #define PI_OFFSET		0x800
    95. 

  95. #define PI_BASE(ch)		(CTL_BASE(ch) + PI_OFFSET)
    96. 

  96. #define PI_REG(ch, n)		(PI_BASE(ch) + (n) * 0x4)
    97. 

  97. 

  98. #define PHY_OFFSET		0x2000
    99. 

  99. #define PHY_BASE(ch)		(CTL_BASE(ch) + PHY_OFFSET)
    100. 

  100. #define PHY_REG(ch, n)		(PHY_BASE(ch) + (n) * 0x4)
    101. 

  101. 

  102. #define MSCH_BASE(ch)		(SERVICE_NOC_1_BASE + (ch) * 0x8000)
    103. 

  103. 

  104. #endif /* ADDRESSMAP_SHARED_H */
    105.