platform.mk 3.5 KB

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  1. #
  2. # Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
  3. #
  4. # SPDX-License-Identifier: BSD-3-Clause
  5. #
  6. RK_PLAT := plat/rockchip
  7. RK_PLAT_SOC := ${RK_PLAT}/${PLAT}
  8. RK_PLAT_COMMON := ${RK_PLAT}/common
  9. DISABLE_BIN_GENERATION := 1
  10. PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \
  11. -I${RK_PLAT_COMMON}/include/ \
  12. -I${RK_PLAT_COMMON}/aarch64/ \
  13. -I${RK_PLAT_COMMON}/drivers/pmu/ \
  14. -I${RK_PLAT_SOC}/ \
  15. -I${RK_PLAT_SOC}/drivers/pmu/ \
  16. -I${RK_PLAT_SOC}/drivers/pwm/ \
  17. -I${RK_PLAT_SOC}/drivers/secure/ \
  18. -I${RK_PLAT_SOC}/drivers/soc/ \
  19. -I${RK_PLAT_SOC}/drivers/dram/ \
  20. -I${RK_PLAT_SOC}/drivers/dp/ \
  21. -I${RK_PLAT_SOC}/include/ \
  22. -I${RK_PLAT_SOC}/include/shared/ \
  23. # Include GICv3 driver files
  24. include drivers/arm/gic/v3/gicv3.mk
  25. RK_GIC_SOURCES := ${GICV3_SOURCES} \
  26. plat/common/plat_gicv3.c \
  27. ${RK_PLAT}/common/rockchip_gicv3.c
  28. PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \
  29. lib/bl_aux_params/bl_aux_params.c \
  30. lib/xlat_tables/xlat_tables_common.c \
  31. lib/xlat_tables/aarch64/xlat_tables.c \
  32. plat/common/aarch64/crash_console_helpers.S \
  33. plat/common/plat_psci_common.c
  34. ifneq (${ENABLE_STACK_PROTECTOR},0)
  35. PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c
  36. endif
  37. BL31_SOURCES += ${RK_GIC_SOURCES} \
  38. drivers/arm/cci/cci.c \
  39. drivers/ti/uart/aarch64/16550_console.S \
  40. drivers/delay_timer/delay_timer.c \
  41. drivers/delay_timer/generic_delay_timer.c \
  42. drivers/gpio/gpio.c \
  43. lib/cpus/aarch64/cortex_a53.S \
  44. lib/cpus/aarch64/cortex_a72.S \
  45. ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
  46. ${RK_PLAT_COMMON}/bl31_plat_setup.c \
  47. ${RK_PLAT_COMMON}/params_setup.c \
  48. ${RK_PLAT_COMMON}/aarch64/pmu_sram_cpus_on.S \
  49. ${RK_PLAT_COMMON}/plat_pm.c \
  50. ${RK_PLAT_COMMON}/plat_topology.c \
  51. ${RK_PLAT_COMMON}/aarch64/platform_common.c \
  52. ${RK_PLAT_COMMON}/rockchip_sip_svc.c \
  53. ${RK_PLAT_SOC}/plat_sip_calls.c \
  54. ${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \
  55. ${RK_PLAT_SOC}/drivers/pmu/pmu.c \
  56. ${RK_PLAT_SOC}/drivers/pmu/pmu_fw.S \
  57. ${RK_PLAT_SOC}/drivers/pmu/m0_ctl.c \
  58. ${RK_PLAT_SOC}/drivers/pwm/pwm.c \
  59. ${RK_PLAT_SOC}/drivers/secure/secure.c \
  60. ${RK_PLAT_SOC}/drivers/soc/soc.c \
  61. ${RK_PLAT_SOC}/drivers/dram/dfs.c \
  62. ${RK_PLAT_SOC}/drivers/dram/dram.c \
  63. ${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c \
  64. ${RK_PLAT_SOC}/drivers/dram/suspend.c
  65. include lib/coreboot/coreboot.mk
  66. include lib/libfdt/libfdt.mk
  67. $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
  68. # Enable workarounds for selected Cortex-A53 erratas.
  69. ERRATA_A53_855873 := 1
  70. # M0 source build
  71. PLAT_M0 := ${PLAT}m0
  72. BUILD_M0 := ${BUILD_PLAT}/m0
  73. RK3399M0FW=${BUILD_M0}/${PLAT_M0}.bin
  74. $(eval $(call add_define_val,RK3399M0FW,\"$(RK3399M0FW)\"))
  75. RK3399M0PMUFW=${BUILD_M0}/${PLAT_M0}pmu.bin
  76. $(eval $(call add_define_val,RK3399M0PMUFW,\"$(RK3399M0PMUFW)\"))
  77. ifdef PLAT_RK_DP_HDCP
  78. BL31_SOURCES += ${RK_PLAT_SOC}/drivers/dp/cdn_dp.c
  79. HDCPFW=${RK_PLAT_SOC}/drivers/dp/hdcp.bin
  80. $(eval $(call add_define_val,HDCPFW,\"$(HDCPFW)\"))
  81. ${BUILD_PLAT}/bl31/cdn_dp.o: CCACHE_EXTRAFILES=$(HDCPFW)
  82. ${RK_PLAT_SOC}/drivers/dp/cdn_dp.c: $(HDCPFW)
  83. endif
  84. # CCACHE_EXTRAFILES is needed because ccache doesn't handle .incbin
  85. export CCACHE_EXTRAFILES
  86. ${BUILD_PLAT}/bl31/pmu_fw.o: CCACHE_EXTRAFILES=$(RK3399M0FW):$(RK3399M0PMUFW)
  87. ${RK_PLAT_SOC}/drivers/pmu/pmu_fw.S: $(RK3399M0FW)
  88. .PHONY: $(RK3399M0FW)
  89. $(RK3399M0FW): | $$(@D)/
  90. $(MAKE) -C ${RK_PLAT_SOC}/drivers/m0 BUILD=$(abspath ${BUILD_PLAT}/m0)
  91. # Do not enable SVE
  92. ENABLE_SVE_FOR_NS := 0