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rpi3
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rpi_hw.h

rpi_hw.h 1.9 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef RPI_HW_H
    8. 

  8. #define RPI_HW_H
    9. 

  9. 

  10. #include <lib/utils_def.h>
    11. 

  11. 

  12. /*
    13. 

  13.  * Peripherals
    14. 

  14.  */
    15. 

  15. 

  16. #define RPI_IO_BASE			ULL(0x3F000000)
    17. 

  17. #define RPI_IO_SIZE			ULL(0x01000000)
    18. 

  18. 

  19. /*
    20. 

  20.  * ARM <-> VideoCore mailboxes
    21. 

  21.  */
    22. 

  22. #define RPI3_MBOX_OFFSET		ULL(0x0000B880)
    23. 

  23. #define RPI3_MBOX_BASE			(RPI_IO_BASE + RPI3_MBOX_OFFSET)
    24. 

  24. 

  25. /*
    26. 

  26.  * Power management, reset controller, watchdog.
    27. 

  27.  */
    28. 

  28. #define RPI3_IO_PM_OFFSET		ULL(0x00100000)
    29. 

  29. #define RPI3_PM_BASE			(RPI_IO_BASE + RPI3_IO_PM_OFFSET)
    30. 

  30. 

  31. /*
    32. 

  32.  * Hardware random number generator.
    33. 

  33.  */
    34. 

  34. #define RPI3_IO_RNG_OFFSET		ULL(0x00104000)
    35. 

  35. #define RPI3_RNG_BASE			(RPI_IO_BASE + RPI3_IO_RNG_OFFSET)
    36. 

  36. 

  37. /*
    38. 

  38.  * Serial ports:
    39. 

  39.  * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART.
    40. 

  40.  * There is also a PL011 UART, multiplexed to the same pins.
    41. 

  41.  */
    42. 

  42. #define RPI3_IO_MINI_UART_OFFSET	ULL(0x00215040)
    43. 

  43. #define RPI3_MINI_UART_BASE		(RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
    44. 

  44. #define RPI3_IO_PL011_UART_OFFSET	ULL(0x00201000)
    45. 

  45. #define RPI3_PL011_UART_BASE		(RPI_IO_BASE + RPI3_IO_PL011_UART_OFFSET)
    46. 

  46. #define RPI3_PL011_UART_CLOCK		ULL(48000000)
    47. 

  47. 

  48. /*
    49. 

  49.  * GPIO controller
    50. 

  50.  */
    51. 

  51. #define RPI3_IO_GPIO_OFFSET		ULL(0x00200000)
    52. 

  52. #define RPI3_GPIO_BASE			(RPI_IO_BASE + RPI3_IO_GPIO_OFFSET)
    53. 

  53. 

  54. /*
    55. 

  55.  * SDHost controller
    56. 

  56.  */
    57. 

  57. #define RPI3_IO_SDHOST_OFFSET           ULL(0x00202000)
    58. 

  58. #define RPI3_SDHOST_BASE                (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET)
    59. 

  59. 

  60. /*
    61. 

  61.  * Local interrupt controller
    62. 

  62.  */
    63. 

  63. #define RPI3_INTC_BASE_ADDRESS			ULL(0x40000000)
    64. 

  64. /* Registers on top of RPI3_INTC_BASE_ADDRESS */
    65. 

  65. #define RPI3_INTC_CONTROL_OFFSET		ULL(0x00000000)
    66. 

  66. #define RPI3_INTC_PRESCALER_OFFSET		ULL(0x00000008)
    67. 

  67. #define RPI3_INTC_MBOX_CONTROL_OFFSET		ULL(0x00000050)
    68. 

  68. #define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ	ULL(0x00000080)
    69. 

  69. #define RPI3_INTC_PENDING_FIQ_OFFSET		ULL(0x00000070)
    70. 

  70. #define RPI3_INTC_PENDING_FIQ_MBOX3		ULL(0x00000080)
    71. 

  71. 

  72. #endif /* RPI_HW_H */
    73.