sq_helpers.S 2.7 KB

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  1. /*
  2. * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <arch.h>
  7. #include <asm_macros.S>
  8. #include <assert_macros.S>
  9. #include <platform_def.h>
  10. .global sq_calc_core_pos
  11. .global plat_my_core_pos
  12. .global platform_mem_init
  13. .global plat_is_my_cpu_primary
  14. .global plat_secondary_cold_boot_setup
  15. .global plat_crash_console_init
  16. .global plat_crash_console_putc
  17. .global plat_crash_console_flush
  18. /*
  19. * unsigned int sq_calc_core_pos(u_register_t mpidr)
  20. * core_pos = (cluster_id * max_cpus_per_cluster) + core_id
  21. */
  22. func sq_calc_core_pos
  23. and x1, x0, #MPIDR_CPU_MASK
  24. and x0, x0, #MPIDR_CLUSTER_MASK
  25. add x0, x1, x0, lsr #7
  26. ret
  27. endfunc sq_calc_core_pos
  28. func plat_my_core_pos
  29. mrs x0, mpidr_el1
  30. b sq_calc_core_pos
  31. endfunc plat_my_core_pos
  32. func platform_mem_init
  33. ret
  34. endfunc platform_mem_init
  35. /*
  36. * Secondary CPUs are placed in a holding pen, waiting for their mailbox
  37. * to be populated. Note that all CPUs share the same mailbox ; therefore,
  38. * populating it will release all CPUs from their holding pen. If
  39. * finer-grained control is needed then this should be handled in the
  40. * code that secondary CPUs jump to.
  41. */
  42. func plat_secondary_cold_boot_setup
  43. #if !RESET_TO_BL31
  44. mov_imm x0, BL2_MAILBOX_BASE
  45. ldr x0, [x0]
  46. #else
  47. ldr x0, sq_sec_entrypoint
  48. #endif
  49. /* Wait until the mailbox gets populated */
  50. poll_mailbox:
  51. cbz x0, 1f
  52. br x0
  53. 1:
  54. wfe
  55. b poll_mailbox
  56. endfunc plat_secondary_cold_boot_setup
  57. /*
  58. * Find out whether the current cpu is the primary
  59. * cpu (applicable only after a cold boot)
  60. */
  61. func plat_is_my_cpu_primary
  62. mov x9, x30
  63. bl plat_my_core_pos
  64. ldr x1, =SQ_BOOT_CFG_ADDR
  65. ldr x1, [x1]
  66. ubfx x1, x1, #PLAT_SQ_PRIMARY_CPU_SHIFT, \
  67. #PLAT_SQ_PRIMARY_CPU_BIT_WIDTH
  68. cmp x0, x1
  69. cset w0, eq
  70. ret x9
  71. endfunc plat_is_my_cpu_primary
  72. /*
  73. * int plat_crash_console_init(void)
  74. * Function to initialize the crash console
  75. * without a C Runtime to print crash report.
  76. * Clobber list : x0, x1, x2
  77. */
  78. func plat_crash_console_init
  79. mov_imm x0, PLAT_SQ_BOOT_UART_BASE
  80. mov_imm x1, PLAT_SQ_BOOT_UART_CLK_IN_HZ
  81. mov_imm x2, SQ_CONSOLE_BAUDRATE
  82. b console_pl011_core_init
  83. endfunc plat_crash_console_init
  84. /*
  85. * int plat_crash_console_putc(int c)
  86. * Function to print a character on the crash
  87. * console without a C Runtime.
  88. * Clobber list : x1, x2
  89. */
  90. func plat_crash_console_putc
  91. mov_imm x1, PLAT_SQ_BOOT_UART_BASE
  92. b console_pl011_core_putc
  93. endfunc plat_crash_console_putc
  94. /*
  95. * void plat_crash_console_flush(int c)
  96. * Function to force a write of all buffered
  97. * data that hasn't been output.
  98. * Out : void.
  99. * Clobber list : x0, x1
  100. */
  101. func plat_crash_console_flush
  102. mov_imm x0, PLAT_SQ_BOOT_UART_BASE
  103. b console_pl011_core_flush
  104. endfunc plat_crash_console_flush