platform.mk 4.9 KB

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  1. #
  2. # Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
  3. # Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
  4. # Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
  5. # Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
  6. #
  7. # SPDX-License-Identifier: BSD-3-Clause
  8. override ERRATA_A53_855873 := 1
  9. ERRATA_A53_1530924 := 1
  10. override PROGRAMMABLE_RESET_ADDRESS := 1
  11. PSCI_EXTENDED_STATE_ID := 1
  12. A53_DISABLE_NON_TEMPORAL_HINT := 0
  13. SEPARATE_CODE_AND_RODATA := 1
  14. ZYNQMP_WDT_RESTART := 0
  15. IPI_CRC_CHECK := 0
  16. override RESET_TO_BL31 := 1
  17. override WARMBOOT_ENABLE_DCACHE_EARLY := 1
  18. ENABLE_LTO := 1
  19. EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
  20. # pncd SPD requires secure SGI to be handled at EL1
  21. ifeq (${SPD}, $(filter ${SPD},pncd tspd opteed))
  22. ifeq (${ZYNQMP_WDT_RESTART},1)
  23. $(error "Error: ZYNQMP_WDT_RESTART and SPD=pncd are incompatible")
  24. endif
  25. override GICV2_G0_FOR_EL3 := 0
  26. else
  27. override GICV2_G0_FOR_EL3 := 1
  28. endif
  29. # Do not enable SVE
  30. ENABLE_SVE_FOR_NS := 0
  31. WORKAROUND_CVE_2017_5715 := 0
  32. ifdef ZYNQMP_ATF_MEM_BASE
  33. $(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
  34. ifndef ZYNQMP_ATF_MEM_SIZE
  35. $(error "ZYNQMP_ATF_MEM_BASE defined without ZYNQMP_ATF_MEM_SIZE")
  36. endif
  37. $(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE))
  38. ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
  39. $(eval $(call add_define,ZYNQMP_ATF_MEM_PROGBITS_SIZE))
  40. endif
  41. # enable assert() when TF-A runs from DDR memory.
  42. ENABLE_ASSERTIONS := 1
  43. endif
  44. ifdef ZYNQMP_BL32_MEM_BASE
  45. $(eval $(call add_define,ZYNQMP_BL32_MEM_BASE))
  46. ifndef ZYNQMP_BL32_MEM_SIZE
  47. $(error "ZYNQMP_BL32_MEM_BASE defined without ZYNQMP_BL32_MEM_SIZE")
  48. endif
  49. $(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE))
  50. endif
  51. ifdef ZYNQMP_WDT_RESTART
  52. $(eval $(call add_define,ZYNQMP_WDT_RESTART))
  53. endif
  54. ifdef ZYNQMP_IPI_CRC_CHECK
  55. $(warning "ZYNQMP_IPI_CRC_CHECK macro is deprecated...instead please use IPI_CRC_CHECK.")
  56. endif
  57. ifdef IPI_CRC_CHECK
  58. $(eval $(call add_define,IPI_CRC_CHECK))
  59. endif
  60. ifdef ZYNQMP_SECURE_EFUSES
  61. $(eval $(call add_define,ZYNQMP_SECURE_EFUSES))
  62. endif
  63. ifdef XILINX_OF_BOARD_DTB_ADDR
  64. $(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
  65. endif
  66. PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
  67. -Iinclude/plat/arm/common/aarch64/ \
  68. -Iplat/xilinx/common/include/ \
  69. -Iplat/xilinx/common/ipi_mailbox_service/ \
  70. -Iplat/xilinx/zynqmp/include/ \
  71. -Iplat/xilinx/zynqmp/pm_service/ \
  72. include lib/libfdt/libfdt.mk
  73. # Include GICv2 driver files
  74. include drivers/arm/gic/v2/gicv2.mk
  75. include lib/xlat_tables_v2/xlat_tables.mk
  76. PLAT_BL_COMMON_SOURCES := drivers/arm/dcc/dcc_console.c \
  77. drivers/delay_timer/delay_timer.c \
  78. drivers/delay_timer/generic_delay_timer.c \
  79. ${GICV2_SOURCES} \
  80. drivers/cadence/uart/aarch64/cdns_console.S \
  81. plat/arm/common/arm_cci.c \
  82. plat/arm/common/arm_common.c \
  83. plat/arm/common/arm_gicv2.c \
  84. plat/common/plat_gicv2.c \
  85. plat/xilinx/common/ipi.c \
  86. plat/xilinx/zynqmp/zynqmp_ipi.c \
  87. plat/common/aarch64/crash_console_helpers.S \
  88. plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \
  89. plat/xilinx/zynqmp/aarch64/zynqmp_common.c \
  90. ${XLAT_TABLES_LIB_SRCS}
  91. ZYNQMP_CONSOLE ?= cadence
  92. ifeq (${ZYNQMP_CONSOLE}, $(filter ${ZYNQMP_CONSOLE},cadence cadence0 cadence1 dcc dtb none))
  93. else
  94. $(error "Please define ZYNQMP_CONSOLE")
  95. endif
  96. $(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE}))
  97. # Runtime console in default console in DEBUG build
  98. ifeq ($(DEBUG), 1)
  99. CONSOLE_RUNTIME ?= cadence
  100. endif
  101. # Runtime console
  102. ifdef CONSOLE_RUNTIME
  103. ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},cadence cadence0 cadence1 dcc dtb))
  104. $(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME}))
  105. else
  106. $(error "Please define CONSOLE_RUNTIME")
  107. endif
  108. endif
  109. # Build PM code as a Library
  110. include plat/xilinx/zynqmp/libpm.mk
  111. BL31_SOURCES += drivers/arm/cci/cci.c \
  112. lib/cpus/aarch64/aem_generic.S \
  113. lib/cpus/aarch64/cortex_a53.S \
  114. plat/common/plat_psci_common.c \
  115. common/fdt_fixup.c \
  116. common/fdt_wrappers.c \
  117. ${LIBFDT_SRCS} \
  118. plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
  119. plat/xilinx/common/plat_startup.c \
  120. plat/xilinx/common/plat_console.c \
  121. plat/xilinx/common/plat_fdt.c \
  122. plat/xilinx/zynqmp/bl31_zynqmp_setup.c \
  123. plat/xilinx/zynqmp/plat_psci.c \
  124. plat/xilinx/zynqmp/plat_zynqmp.c \
  125. plat/xilinx/zynqmp/plat_topology.c \
  126. plat/xilinx/zynqmp/sip_svc_setup.c
  127. ifeq (${SDEI_SUPPORT},1)
  128. BL31_SOURCES += plat/xilinx/zynqmp/zynqmp_ehf.c \
  129. plat/xilinx/zynqmp/zynqmp_sdei.c
  130. endif
  131. BL31_CPPFLAGS += -fno-jump-tables
  132. TF_CFLAGS_aarch64 += -mbranch-protection=none
  133. ifdef CUSTOM_PKG_PATH
  134. include $(CUSTOM_PKG_PATH)/custom_pkg.mk
  135. else
  136. BL31_SOURCES += plat/xilinx/zynqmp/custom_sip_svc.c
  137. endif
  138. ifneq (${RESET_TO_BL31},1)
  139. $(error "Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1.")
  140. endif