hikey960_bl31_setup.c 7.0 KB

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  1. /*
  2. * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <assert.h>
  7. #include <errno.h>
  8. #include <platform_def.h>
  9. #include <arch_helpers.h>
  10. #include <bl31/interrupt_mgmt.h>
  11. #include <common/bl_common.h>
  12. #include <common/debug.h>
  13. #include <common/interrupt_props.h>
  14. #include <drivers/arm/cci.h>
  15. #include <drivers/arm/gicv2.h>
  16. #include <drivers/arm/pl011.h>
  17. #include <drivers/console.h>
  18. #include <drivers/generic_delay_timer.h>
  19. #include <lib/mmio.h>
  20. #include <lib/xlat_tables/xlat_tables_v2.h>
  21. #include <plat/common/platform.h>
  22. #include <services/el3_spmc_ffa_memory.h>
  23. #include <hi3660.h>
  24. #include <hisi_ipc.h>
  25. #include "hikey960_def.h"
  26. #include "hikey960_private.h"
  27. static entry_point_info_t bl32_ep_info;
  28. static entry_point_info_t bl33_ep_info;
  29. static console_t console;
  30. /* fastboot serial number consumed by Kinibi SPD/LP for gpd.tee.deviceID. */
  31. uint64_t fastboot_serno;
  32. /******************************************************************************
  33. * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
  34. * interrupts.
  35. *****************************************************************************/
  36. static const interrupt_prop_t g0_interrupt_props[] = {
  37. INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
  38. GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
  39. INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
  40. GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
  41. };
  42. const gicv2_driver_data_t hikey960_gic_data = {
  43. .gicd_base = GICD_REG_BASE,
  44. .gicc_base = GICC_REG_BASE,
  45. .interrupt_props = g0_interrupt_props,
  46. .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
  47. };
  48. static const int cci_map[] = {
  49. CCI400_SL_IFACE3_CLUSTER_IX,
  50. CCI400_SL_IFACE4_CLUSTER_IX
  51. };
  52. entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  53. {
  54. entry_point_info_t *next_image_info;
  55. next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
  56. /* None of the images on this platform can have 0x0 as the entrypoint */
  57. if (next_image_info->pc)
  58. return next_image_info;
  59. return NULL;
  60. }
  61. void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
  62. u_register_t arg2, u_register_t arg3)
  63. {
  64. unsigned int id, uart_base;
  65. void *from_bl2;
  66. plat_params_from_bl2_t *plat_params_from_bl2 = (plat_params_from_bl2_t *) arg1;
  67. from_bl2 = (void *) arg0;
  68. generic_delay_timer_init();
  69. hikey960_read_boardid(&id);
  70. if (id == 5300)
  71. uart_base = PL011_UART5_BASE;
  72. else
  73. uart_base = PL011_UART6_BASE;
  74. /* Initialize the console to provide early debug support */
  75. console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ,
  76. PL011_BAUDRATE, &console);
  77. /* Initialize CCI driver */
  78. cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map));
  79. cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
  80. /* Fastboot serial number passed from BL2 as a platform parameter */
  81. fastboot_serno = plat_params_from_bl2->fastboot_serno;
  82. INFO("BL31: fastboot_serno %lx\n", fastboot_serno);
  83. /*
  84. * Check params passed from BL2 should not be NULL,
  85. */
  86. bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
  87. assert(params_from_bl2 != NULL);
  88. assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
  89. assert(params_from_bl2->h.version >= VERSION_2);
  90. bl_params_node_t *bl_params = params_from_bl2->head;
  91. /*
  92. * Copy BL33 and BL32 (if present), entry point information.
  93. * They are stored in Secure RAM, in BL2's address space.
  94. */
  95. while (bl_params) {
  96. if (bl_params->image_id == BL32_IMAGE_ID)
  97. bl32_ep_info = *bl_params->ep_info;
  98. if (bl_params->image_id == BL33_IMAGE_ID)
  99. bl33_ep_info = *bl_params->ep_info;
  100. bl_params = bl_params->next_params_info;
  101. }
  102. if (bl33_ep_info.pc == 0)
  103. panic();
  104. }
  105. void bl31_plat_arch_setup(void)
  106. {
  107. #if SPMC_AT_EL3
  108. mmap_add_region(DDR2_SEC_BASE, DDR2_SEC_BASE, DDR2_SEC_SIZE,
  109. MT_MEMORY | MT_RW | MT_SECURE);
  110. #endif
  111. hikey960_init_mmu_el3(BL31_BASE,
  112. BL31_LIMIT - BL31_BASE,
  113. BL_CODE_BASE,
  114. BL_CODE_END,
  115. BL_COHERENT_RAM_BASE,
  116. BL_COHERENT_RAM_END);
  117. }
  118. static void hikey960_edma_init(void)
  119. {
  120. int i;
  121. uint32_t non_secure;
  122. non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC;
  123. mmio_write_32(EDMAC_SEC_CTRL, non_secure);
  124. /* Channel 0 is reserved for LPM3, keep secure */
  125. for (i = 1; i < EDMAC_CHANNEL_NUMS; i++) {
  126. mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18));
  127. }
  128. }
  129. static void hikey960_iomcu_dma_init(void)
  130. {
  131. int i;
  132. uint32_t non_secure;
  133. non_secure = IOMCU_DMAC_SEC_CTRL_INTR_SEC | IOMCU_DMAC_SEC_CTRL_GLOBAL_SEC;
  134. mmio_write_32(IOMCU_DMAC_SEC_CTRL, non_secure);
  135. /* channels 0-3 are reserved */
  136. for (i = 4; i < IOMCU_DMAC_CHANNEL_NUMS; i++) {
  137. mmio_write_32(IOMCU_DMAC_AXI_CONF(i), IOMCU_DMAC_AXI_CONF_ARPROT_NS |
  138. IOMCU_DMAC_AXI_CONF_AWPROT_NS);
  139. }
  140. }
  141. #if SPMC_AT_EL3
  142. /*
  143. * On the hikey960 platform when using the EL3 SPMC implementation allocate the
  144. * datastore for tracking shared memory descriptors in the RAM2 DRAM section
  145. * to ensure sufficient storage can be allocated.
  146. * Provide an implementation of the accessor method to allow the datastore
  147. * details to be retrieved by the SPMC.
  148. * The SPMC will take care of initializing the memory region.
  149. */
  150. #define SPMC_SHARED_MEMORY_OBJ_SIZE (512 * 1024)
  151. __section(".ram2_region") uint8_t plat_spmc_shmem_datastore[SPMC_SHARED_MEMORY_OBJ_SIZE];
  152. int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size)
  153. {
  154. *datastore = plat_spmc_shmem_datastore;
  155. *size = SPMC_SHARED_MEMORY_OBJ_SIZE;
  156. return 0;
  157. }
  158. /*
  159. * Add dummy implementations of memory management related platform hooks.
  160. * These can be used to implement platform specific functionality to support
  161. * a memory sharing/lending operation.
  162. *
  163. * Note: The hooks must be located as part of the initial share request and
  164. * final reclaim to prevent order dependencies with operations that may take
  165. * place in the normal world without visibility of the SPMC.
  166. */
  167. int plat_spmc_shmem_begin(struct ffa_mtd *desc)
  168. {
  169. return 0;
  170. }
  171. int plat_spmc_shmem_reclaim(struct ffa_mtd *desc)
  172. {
  173. return 0;
  174. }
  175. #endif
  176. void bl31_platform_setup(void)
  177. {
  178. /* Initialize the GIC driver, cpu and distributor interfaces */
  179. gicv2_driver_init(&hikey960_gic_data);
  180. gicv2_distif_init();
  181. gicv2_pcpu_distif_init();
  182. gicv2_cpuif_enable();
  183. hikey960_edma_init();
  184. hikey960_iomcu_dma_init();
  185. hikey960_gpio_init();
  186. hisi_ipc_init();
  187. }
  188. #ifdef SPD_none
  189. static uint64_t hikey_debug_fiq_handler(uint32_t id,
  190. uint32_t flags,
  191. void *handle,
  192. void *cookie)
  193. {
  194. int intr, intr_raw;
  195. /* Acknowledge interrupt */
  196. intr_raw = plat_ic_acknowledge_interrupt();
  197. intr = plat_ic_get_interrupt_id(intr_raw);
  198. ERROR("Invalid interrupt: intr=%d\n", intr);
  199. console_flush();
  200. panic();
  201. return 0;
  202. }
  203. #elif defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
  204. /*
  205. * A dummy implementation of the platform handler for Group0 secure interrupt.
  206. */
  207. int plat_spmd_handle_group0_interrupt(uint32_t intid)
  208. {
  209. (void)intid;
  210. return -1;
  211. }
  212. #endif
  213. void bl31_plat_runtime_setup(void)
  214. {
  215. #ifdef SPD_none
  216. uint32_t flags;
  217. int32_t rc;
  218. flags = 0;
  219. set_interrupt_rm_flag(flags, NON_SECURE);
  220. rc = register_interrupt_type_handler(INTR_TYPE_S_EL1,
  221. hikey_debug_fiq_handler,
  222. flags);
  223. if (rc != 0)
  224. panic();
  225. #endif
  226. }