platform.mk 2.8 KB

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  1. #
  2. # Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
  3. # Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
  4. #
  5. # SPDX-License-Identifier: BSD-3-Clause
  6. #
  7. PLAT_INCLUDES := \
  8. -Iplat/intel/soc/stratix10/include/ \
  9. -Iplat/intel/soc/common/drivers/ \
  10. -Iplat/intel/soc/common/include/
  11. # Include GICv2 driver files
  12. include drivers/arm/gic/v2/gicv2.mk
  13. AGX_GICv2_SOURCES := \
  14. ${GICV2_SOURCES} \
  15. plat/common/plat_gicv2.c
  16. PLAT_BL_COMMON_SOURCES := \
  17. ${AGX_GICv2_SOURCES} \
  18. drivers/delay_timer/delay_timer.c \
  19. drivers/delay_timer/generic_delay_timer.c \
  20. drivers/ti/uart/aarch64/16550_console.S \
  21. lib/xlat_tables/aarch64/xlat_tables.c \
  22. lib/xlat_tables/xlat_tables_common.c \
  23. plat/intel/soc/common/aarch64/platform_common.c \
  24. plat/intel/soc/common/aarch64/plat_helpers.S \
  25. plat/intel/soc/common/socfpga_delay_timer.c \
  26. plat/intel/soc/common/soc/socfpga_firewall.c
  27. BL2_SOURCES += \
  28. common/desc_image_load.c \
  29. drivers/mmc/mmc.c \
  30. drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
  31. drivers/io/io_storage.c \
  32. drivers/io/io_block.c \
  33. drivers/io/io_fip.c \
  34. drivers/partition/partition.c \
  35. drivers/partition/gpt.c \
  36. drivers/synopsys/emmc/dw_mmc.c \
  37. lib/cpus/aarch64/cortex_a53.S \
  38. plat/intel/soc/stratix10/bl2_plat_setup.c \
  39. plat/intel/soc/stratix10/soc/s10_clock_manager.c \
  40. plat/intel/soc/stratix10/soc/s10_memory_controller.c \
  41. plat/intel/soc/stratix10/soc/s10_mmc.c \
  42. plat/intel/soc/stratix10/soc/s10_pinmux.c \
  43. plat/intel/soc/common/bl2_plat_mem_params_desc.c \
  44. plat/intel/soc/common/socfpga_image_load.c \
  45. plat/intel/soc/common/socfpga_storage.c \
  46. plat/intel/soc/common/soc/socfpga_emac.c \
  47. plat/intel/soc/common/soc/socfpga_handoff.c \
  48. plat/intel/soc/common/soc/socfpga_mailbox.c \
  49. plat/intel/soc/common/soc/socfpga_reset_manager.c \
  50. plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
  51. plat/intel/soc/common/drivers/ddr/ddr.c \
  52. plat/intel/soc/common/drivers/wdt/watchdog.c
  53. include lib/zlib/zlib.mk
  54. PLAT_INCLUDES += -Ilib/zlib
  55. BL2_SOURCES += $(ZLIB_SOURCES)
  56. BL31_SOURCES += \
  57. drivers/arm/cci/cci.c \
  58. lib/cpus/aarch64/aem_generic.S \
  59. lib/cpus/aarch64/cortex_a53.S \
  60. plat/common/plat_psci_common.c \
  61. plat/intel/soc/stratix10/soc/s10_clock_manager.c \
  62. plat/intel/soc/stratix10/bl31_plat_setup.c \
  63. plat/intel/soc/common/socfpga_psci.c \
  64. plat/intel/soc/common/socfpga_sip_svc.c \
  65. plat/intel/soc/common/socfpga_sip_svc_v2.c \
  66. plat/intel/soc/common/socfpga_topology.c \
  67. plat/intel/soc/common/sip/socfpga_sip_ecc.c \
  68. plat/intel/soc/common/sip/socfpga_sip_fcs.c \
  69. plat/intel/soc/common/soc/socfpga_mailbox.c \
  70. plat/intel/soc/common/soc/socfpga_reset_manager.c
  71. $(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
  72. PROGRAMMABLE_RESET_ADDRESS := 0
  73. RESET_TO_BL2 := 1
  74. USE_COHERENT_MEM := 1