arm-trusted-firmware/plat/nxp/soc-ls1028a/soc.def

#
# Copyright 2018-2021 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
#
#
#------------------------------------------------------------------------------
#
# This file contains the basic architecture definitions that drive the build
#
# -----------------------------------------------------------------------------

CORE_TYPE	:=	a72

CACHE_LINE	:=	6

# Set to GIC400 or GIC500
GIC		:=	GIC500

# Set to CCI400 or CCN504 or CCN508
INTERCONNECT	:=	CCI400

# Layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
CHASSIS		:=	3_2

# TZC used is TZC380 or TZC400
TZC_ID		:=	TZC400

# CONSOLE is NS16550 or PL011
CONSOLE		:=	NS16550

# DDR PHY generation to be used
PLAT_DDR_PHY	:=	PHY_GEN1

PHYS_SYS	:=	64

# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
# Input to CST create_hdr_esbc tool
CSF_HDR_SZ	:=	0x3000

# In IMAGE_BL2, compile time flag for handling Cache coherency
# with CAAM for BL2 running from OCRAM
SEC_MEM_NON_COHERENT	:=	yes

# OCRAM MAP for BL2
# Before BL2
# 0x18000000 - 0x18009fff -> Used by ROM code
# 0x1800a000 - 0x1800dfff -> CSF header for BL2
# For FlexSFlexSPI boot
# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary
# For SD boot
# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary
# 0x18030000 - 0x18040000 -> Reserved for SD buffer
OCRAM_START_ADDR	:=	0x18000000
OCRAM_SIZE		:=	0x40000

# Area of OCRAM reserved by ROM code
NXP_ROM_RSVD	:=	0xa000

# Location of BL2 on OCRAM
BL2_BASE_ADDR	:=	$(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) )))

# Covert to HEX to be used by create_pbl.mk
BL2_BASE	:=	$(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))

# BL2_HDR_LOC is at  (BL2_BASE + NXP_ROM_RSVD)
# This value BL2_HDR_LOC + CSF_HDR_SZ should not
# overalp with BL2_BASE
# Input to CST create_hdr_isbc tool
BL2_HDR_LOC	:=	0x1800A000

# SoC ERRATAS to be enabled

# DDR ERRATA
ERRATA_DDR_A009803	:=	1
ERRATA_DDR_A009942	:=	1
ERRATA_DDR_A010165	:=	1

# Enable dynamic memory mapping
PLAT_XLAT_TABLES_DYNAMIC	:=	1

# Define Endianness of each module
NXP_GUR_ENDIANNESS	:=	LE
NXP_DDR_ENDIANNESS	:=	LE
NXP_SEC_ENDIANNESS	:=	LE
NXP_SFP_ENDIANNESS	:=	LE
NXP_SNVS_ENDIANNESS	:=	LE
NXP_ESDHC_ENDIANNESS	:=	LE
NXP_QSPI_ENDIANNESS	:=	LE
NXP_FSPI_ENDIANNESS	:=	LE
NXP_SCFG_ENDIANNESS	:=	LE
NXP_GPIO_ENDIANNESS	:=	LE

NXP_SFP_VER		:=	3_4

# OCRAM ECC Enabled
OCRAM_ECC_EN		:=	yes