soc.def 1.9 KB

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  1. #
  2. # Copyright 2022 NXP
  3. #
  4. # SPDX-License-Identifier: BSD-3-Clause
  5. #
  6. #
  7. #------------------------------------------------------------------------------
  8. #
  9. # This file contains the basic architecture definitions that drive the build
  10. #
  11. # -----------------------------------------------------------------------------
  12. CORE_TYPE := a53
  13. CACHE_LINE := 6
  14. # Set to GIC400 or GIC500
  15. GIC := GIC500
  16. # Set to CCI400 or CCN504 or CCN508
  17. INTERCONNECT := CCI400
  18. # Select the DDR PHY generation to be used
  19. PLAT_DDR_PHY := PHY_GEN1
  20. PHYS_SYS := 64
  21. # Indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
  22. CHASSIS := 3
  23. # TZC IP Details TZC used is TZC380 or TZC400
  24. TZC_ID := TZC400
  25. # CONSOLE Details available is NS16550 or PL011
  26. CONSOLE := NS16550
  27. NXP_SFP_VER := 3_4
  28. # In IMAGE_BL2, compile time flag for handling Cache coherency
  29. # with CAAM for BL2 running from OCRAM
  30. SEC_MEM_NON_COHERENT := yes
  31. # OCRAM MAP for BL2
  32. # Before BL2
  33. # 0x18000000 - 0x18009fff -> Used by ROM code, (TBD - can it be used for xlat tables)
  34. # 0x1800a000 - 0x1801Cfff -> Reserved for BL2 binary (76 KB)
  35. # 0x1801D000 - 0x1801ffff -> CSF header for BL2 (12 KB)
  36. OCRAM_START_ADDR := 0x18000000
  37. OCRAM_SIZE := 0x20000
  38. CSF_HDR_SZ := 0x3000
  39. # Area of OCRAM reserved by ROM code
  40. NXP_ROM_RSVD := 0xa000
  41. # Input to CST create_hdr_isbc tool
  42. BL2_HDR_LOC := 0x1801D000
  43. # Location of BL2 on OCRAM
  44. # BL2_BASE=OCRAM_START_ADDR+NXP_ROM_RSVD
  45. BL2_BASE := 0x1800a000
  46. # SoC ERRATUM to be enabled
  47. # ARM Erratum
  48. ERRATA_A53_855873 := 1
  49. # DDR Erratum
  50. ERRATA_DDR_A008511 := 1
  51. ERRATA_DDR_A009803 := 1
  52. ERRATA_DDR_A009942 := 1
  53. ERRATA_DDR_A010165 := 1
  54. # Define Endianness of each module
  55. NXP_ESDHC_ENDIANNESS := LE
  56. NXP_SFP_ENDIANNESS := LE
  57. NXP_GPIO_ENDIANNESS := LE
  58. NXP_SNVS_ENDIANNESS := LE
  59. NXP_GUR_ENDIANNESS := LE
  60. NXP_SEC_ENDIANNESS := LE
  61. NXP_DDR_ENDIANNESS := LE
  62. NXP_QSPI_ENDIANNESS := LE
  63. # OCRAM ECC Enabled
  64. OCRAM_ECC_EN := yes