psci_main.c 11 KB

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  1. /*
  2. * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <arch.h>
  7. #include <arch_helpers.h>
  8. #include <assert.h>
  9. #include <debug.h>
  10. #include <platform.h>
  11. #include <pmf.h>
  12. #include <runtime_instr.h>
  13. #include <smcc.h>
  14. #include <string.h>
  15. #include "psci_private.h"
  16. /*******************************************************************************
  17. * PSCI frontend api for servicing SMCs. Described in the PSCI spec.
  18. ******************************************************************************/
  19. int psci_cpu_on(u_register_t target_cpu,
  20. uintptr_t entrypoint,
  21. u_register_t context_id)
  22. {
  23. int rc;
  24. entry_point_info_t ep;
  25. /* Determine if the cpu exists of not */
  26. rc = psci_validate_mpidr(target_cpu);
  27. if (rc != PSCI_E_SUCCESS)
  28. return PSCI_E_INVALID_PARAMS;
  29. /* Validate the entry point and get the entry_point_info */
  30. rc = psci_validate_entry_point(&ep, entrypoint, context_id);
  31. if (rc != PSCI_E_SUCCESS)
  32. return rc;
  33. /*
  34. * To turn this cpu on, specify which power
  35. * levels need to be turned on
  36. */
  37. return psci_cpu_on_start(target_cpu, &ep);
  38. }
  39. unsigned int psci_version(void)
  40. {
  41. return PSCI_MAJOR_VER | PSCI_MINOR_VER;
  42. }
  43. int psci_cpu_suspend(unsigned int power_state,
  44. uintptr_t entrypoint,
  45. u_register_t context_id)
  46. {
  47. int rc;
  48. unsigned int target_pwrlvl, is_power_down_state;
  49. entry_point_info_t ep;
  50. psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
  51. plat_local_state_t cpu_pd_state;
  52. /* Validate the power_state parameter */
  53. rc = psci_validate_power_state(power_state, &state_info);
  54. if (rc != PSCI_E_SUCCESS) {
  55. assert(rc == PSCI_E_INVALID_PARAMS);
  56. return rc;
  57. }
  58. /*
  59. * Get the value of the state type bit from the power state parameter.
  60. */
  61. is_power_down_state = psci_get_pstate_type(power_state);
  62. /* Sanity check the requested suspend levels */
  63. assert(psci_validate_suspend_req(&state_info, is_power_down_state)
  64. == PSCI_E_SUCCESS);
  65. target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
  66. if (target_pwrlvl == PSCI_INVALID_PWR_LVL) {
  67. ERROR("Invalid target power level for suspend operation\n");
  68. panic();
  69. }
  70. /* Fast path for CPU standby.*/
  71. if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
  72. if (!psci_plat_pm_ops->cpu_standby)
  73. return PSCI_E_INVALID_PARAMS;
  74. /*
  75. * Set the state of the CPU power domain to the platform
  76. * specific retention state and enter the standby state.
  77. */
  78. cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
  79. psci_set_cpu_local_state(cpu_pd_state);
  80. #if ENABLE_PSCI_STAT
  81. plat_psci_stat_accounting_start(&state_info);
  82. #endif
  83. #if ENABLE_RUNTIME_INSTRUMENTATION
  84. PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
  85. RT_INSTR_ENTER_HW_LOW_PWR,
  86. PMF_NO_CACHE_MAINT);
  87. #endif
  88. psci_plat_pm_ops->cpu_standby(cpu_pd_state);
  89. /* Upon exit from standby, set the state back to RUN. */
  90. psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
  91. #if ENABLE_RUNTIME_INSTRUMENTATION
  92. PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
  93. RT_INSTR_EXIT_HW_LOW_PWR,
  94. PMF_NO_CACHE_MAINT);
  95. #endif
  96. #if ENABLE_PSCI_STAT
  97. plat_psci_stat_accounting_stop(&state_info);
  98. /* Update PSCI stats */
  99. psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info);
  100. #endif
  101. return PSCI_E_SUCCESS;
  102. }
  103. /*
  104. * If a power down state has been requested, we need to verify entry
  105. * point and program entry information.
  106. */
  107. if (is_power_down_state) {
  108. rc = psci_validate_entry_point(&ep, entrypoint, context_id);
  109. if (rc != PSCI_E_SUCCESS)
  110. return rc;
  111. }
  112. /*
  113. * Do what is needed to enter the power down state. Upon success,
  114. * enter the final wfi which will power down this CPU. This function
  115. * might return if the power down was abandoned for any reason, e.g.
  116. * arrival of an interrupt
  117. */
  118. psci_cpu_suspend_start(&ep,
  119. target_pwrlvl,
  120. &state_info,
  121. is_power_down_state);
  122. return PSCI_E_SUCCESS;
  123. }
  124. int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
  125. {
  126. int rc;
  127. psci_power_state_t state_info;
  128. entry_point_info_t ep;
  129. /* Check if the current CPU is the last ON CPU in the system */
  130. if (!psci_is_last_on_cpu())
  131. return PSCI_E_DENIED;
  132. /* Validate the entry point and get the entry_point_info */
  133. rc = psci_validate_entry_point(&ep, entrypoint, context_id);
  134. if (rc != PSCI_E_SUCCESS)
  135. return rc;
  136. /* Query the psci_power_state for system suspend */
  137. psci_query_sys_suspend_pwrstate(&state_info);
  138. /* Ensure that the psci_power_state makes sense */
  139. assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL);
  140. assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
  141. == PSCI_E_SUCCESS);
  142. assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]));
  143. /*
  144. * Do what is needed to enter the system suspend state. This function
  145. * might return if the power down was abandoned for any reason, e.g.
  146. * arrival of an interrupt
  147. */
  148. psci_cpu_suspend_start(&ep,
  149. PLAT_MAX_PWR_LVL,
  150. &state_info,
  151. PSTATE_TYPE_POWERDOWN);
  152. return PSCI_E_SUCCESS;
  153. }
  154. int psci_cpu_off(void)
  155. {
  156. int rc;
  157. unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL;
  158. /*
  159. * Do what is needed to power off this CPU and possible higher power
  160. * levels if it able to do so. Upon success, enter the final wfi
  161. * which will power down this CPU.
  162. */
  163. rc = psci_do_cpu_off(target_pwrlvl);
  164. /*
  165. * The only error cpu_off can return is E_DENIED. So check if that's
  166. * indeed the case.
  167. */
  168. assert(rc == PSCI_E_DENIED);
  169. return rc;
  170. }
  171. int psci_affinity_info(u_register_t target_affinity,
  172. unsigned int lowest_affinity_level)
  173. {
  174. int target_idx;
  175. /* We dont support level higher than PSCI_CPU_PWR_LVL */
  176. if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
  177. return PSCI_E_INVALID_PARAMS;
  178. /* Calculate the cpu index of the target */
  179. target_idx = plat_core_pos_by_mpidr(target_affinity);
  180. if (target_idx == -1)
  181. return PSCI_E_INVALID_PARAMS;
  182. return psci_get_aff_info_state_by_idx(target_idx);
  183. }
  184. int psci_migrate(u_register_t target_cpu)
  185. {
  186. int rc;
  187. u_register_t resident_cpu_mpidr;
  188. rc = psci_spd_migrate_info(&resident_cpu_mpidr);
  189. if (rc != PSCI_TOS_UP_MIG_CAP)
  190. return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
  191. PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
  192. /*
  193. * Migrate should only be invoked on the CPU where
  194. * the Secure OS is resident.
  195. */
  196. if (resident_cpu_mpidr != read_mpidr_el1())
  197. return PSCI_E_NOT_PRESENT;
  198. /* Check the validity of the specified target cpu */
  199. rc = psci_validate_mpidr(target_cpu);
  200. if (rc != PSCI_E_SUCCESS)
  201. return PSCI_E_INVALID_PARAMS;
  202. assert(psci_spd_pm && psci_spd_pm->svc_migrate);
  203. rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
  204. assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
  205. return rc;
  206. }
  207. int psci_migrate_info_type(void)
  208. {
  209. u_register_t resident_cpu_mpidr;
  210. return psci_spd_migrate_info(&resident_cpu_mpidr);
  211. }
  212. long psci_migrate_info_up_cpu(void)
  213. {
  214. u_register_t resident_cpu_mpidr;
  215. int rc;
  216. /*
  217. * Return value of this depends upon what
  218. * psci_spd_migrate_info() returns.
  219. */
  220. rc = psci_spd_migrate_info(&resident_cpu_mpidr);
  221. if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP)
  222. return PSCI_E_INVALID_PARAMS;
  223. return resident_cpu_mpidr;
  224. }
  225. int psci_node_hw_state(u_register_t target_cpu,
  226. unsigned int power_level)
  227. {
  228. int rc;
  229. /* Validate target_cpu */
  230. rc = psci_validate_mpidr(target_cpu);
  231. if (rc != PSCI_E_SUCCESS)
  232. return PSCI_E_INVALID_PARAMS;
  233. /* Validate power_level against PLAT_MAX_PWR_LVL */
  234. if (power_level > PLAT_MAX_PWR_LVL)
  235. return PSCI_E_INVALID_PARAMS;
  236. /*
  237. * Dispatch this call to platform to query power controller, and pass on
  238. * to the caller what it returns
  239. */
  240. assert(psci_plat_pm_ops->get_node_hw_state);
  241. rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level);
  242. assert((rc >= HW_ON && rc <= HW_STANDBY) || rc == PSCI_E_NOT_SUPPORTED
  243. || rc == PSCI_E_INVALID_PARAMS);
  244. return rc;
  245. }
  246. int psci_features(unsigned int psci_fid)
  247. {
  248. unsigned int local_caps = psci_caps;
  249. /* Check if it is a 64 bit function */
  250. if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
  251. local_caps &= PSCI_CAP_64BIT_MASK;
  252. /* Check for invalid fid */
  253. if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
  254. && is_psci_fid(psci_fid)))
  255. return PSCI_E_NOT_SUPPORTED;
  256. /* Check if the psci fid is supported or not */
  257. if (!(local_caps & define_psci_cap(psci_fid)))
  258. return PSCI_E_NOT_SUPPORTED;
  259. /* Format the feature flags */
  260. if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 ||
  261. psci_fid == PSCI_CPU_SUSPEND_AARCH64) {
  262. /*
  263. * The trusted firmware does not support OS Initiated Mode.
  264. */
  265. return (FF_PSTATE << FF_PSTATE_SHIFT) |
  266. ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT);
  267. }
  268. /* Return 0 for all other fid's */
  269. return PSCI_E_SUCCESS;
  270. }
  271. /*******************************************************************************
  272. * PSCI top level handler for servicing SMCs.
  273. ******************************************************************************/
  274. u_register_t psci_smc_handler(uint32_t smc_fid,
  275. u_register_t x1,
  276. u_register_t x2,
  277. u_register_t x3,
  278. u_register_t x4,
  279. void *cookie,
  280. void *handle,
  281. u_register_t flags)
  282. {
  283. if (is_caller_secure(flags))
  284. return SMC_UNK;
  285. /* Check the fid against the capabilities */
  286. if (!(psci_caps & define_psci_cap(smc_fid)))
  287. return SMC_UNK;
  288. if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
  289. /* 32-bit PSCI function, clear top parameter bits */
  290. x1 = (uint32_t)x1;
  291. x2 = (uint32_t)x2;
  292. x3 = (uint32_t)x3;
  293. switch (smc_fid) {
  294. case PSCI_VERSION:
  295. return psci_version();
  296. case PSCI_CPU_OFF:
  297. return psci_cpu_off();
  298. case PSCI_CPU_SUSPEND_AARCH32:
  299. return psci_cpu_suspend(x1, x2, x3);
  300. case PSCI_CPU_ON_AARCH32:
  301. return psci_cpu_on(x1, x2, x3);
  302. case PSCI_AFFINITY_INFO_AARCH32:
  303. return psci_affinity_info(x1, x2);
  304. case PSCI_MIG_AARCH32:
  305. return psci_migrate(x1);
  306. case PSCI_MIG_INFO_TYPE:
  307. return psci_migrate_info_type();
  308. case PSCI_MIG_INFO_UP_CPU_AARCH32:
  309. return psci_migrate_info_up_cpu();
  310. case PSCI_NODE_HW_STATE_AARCH32:
  311. return psci_node_hw_state(x1, x2);
  312. case PSCI_SYSTEM_SUSPEND_AARCH32:
  313. return psci_system_suspend(x1, x2);
  314. case PSCI_SYSTEM_OFF:
  315. psci_system_off();
  316. /* We should never return from psci_system_off() */
  317. case PSCI_SYSTEM_RESET:
  318. psci_system_reset();
  319. /* We should never return from psci_system_reset() */
  320. case PSCI_FEATURES:
  321. return psci_features(x1);
  322. #if ENABLE_PSCI_STAT
  323. case PSCI_STAT_RESIDENCY_AARCH32:
  324. return psci_stat_residency(x1, x2);
  325. case PSCI_STAT_COUNT_AARCH32:
  326. return psci_stat_count(x1, x2);
  327. #endif
  328. default:
  329. break;
  330. }
  331. } else {
  332. /* 64-bit PSCI function */
  333. switch (smc_fid) {
  334. case PSCI_CPU_SUSPEND_AARCH64:
  335. return psci_cpu_suspend(x1, x2, x3);
  336. case PSCI_CPU_ON_AARCH64:
  337. return psci_cpu_on(x1, x2, x3);
  338. case PSCI_AFFINITY_INFO_AARCH64:
  339. return psci_affinity_info(x1, x2);
  340. case PSCI_MIG_AARCH64:
  341. return psci_migrate(x1);
  342. case PSCI_MIG_INFO_UP_CPU_AARCH64:
  343. return psci_migrate_info_up_cpu();
  344. case PSCI_NODE_HW_STATE_AARCH64:
  345. return psci_node_hw_state(x1, x2);
  346. case PSCI_SYSTEM_SUSPEND_AARCH64:
  347. return psci_system_suspend(x1, x2);
  348. #if ENABLE_PSCI_STAT
  349. case PSCI_STAT_RESIDENCY_AARCH64:
  350. return psci_stat_residency(x1, x2);
  351. case PSCI_STAT_COUNT_AARCH64:
  352. return psci_stat_count(x1, x2);
  353. #endif
  354. default:
  355. break;
  356. }
  357. }
  358. WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid);
  359. return SMC_UNK;
  360. }