phy.c 73 KB

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  1. /*
  2. * Copyright 2021-2022 NXP
  3. * SPDX-License-Identifier: BSD-3-Clause
  4. *
  5. */
  6. #include <errno.h>
  7. #include <stdint.h>
  8. #include <stdio.h>
  9. #include <stdlib.h>
  10. #include <string.h>
  11. #include <common/debug.h>
  12. #include "csr.h"
  13. #include <ddr.h>
  14. #include "ddr4fw.h"
  15. #include <drivers/delay_timer.h>
  16. #ifdef NXP_WARM_BOOT
  17. #include <fspi_api.h>
  18. #endif
  19. #include "input.h"
  20. #include <lib/mmio.h>
  21. #include <lib/utils.h>
  22. #include <lib/xlat_tables/xlat_tables_v2.h>
  23. #ifdef DDR_PHY_DEBUG
  24. #include "messages.h"
  25. #endif
  26. #ifdef NXP_WARM_BOOT
  27. #include "phy.h"
  28. #endif
  29. #include "pie.h"
  30. #define TIMEOUTDEFAULT 500
  31. #define MAP_PHY_ADDR(pstate, n, instance, offset, c) \
  32. ((((pstate * n) + instance + c) << 12) + offset)
  33. static uint32_t map_phy_addr_space(uint32_t addr)
  34. {
  35. /* 23 bit addressing */
  36. uint32_t pstate = (addr & U(0x700000)) >> 20U; /* bit 22:20 */
  37. uint32_t block_type = (addr & U(0x0f0000)) >> 16U; /* bit 19:16 */
  38. uint32_t instance = (addr & U(0x00f000)) >> 12U; /* bit 15:12 */
  39. uint32_t offset = (addr & U(0x000fff)); /* bit 11:0 */
  40. switch (block_type) {
  41. case 0x0: /* 0x0 : ANIB */
  42. return MAP_PHY_ADDR(pstate, 12, instance, offset, 0);
  43. case 0x1: /* 0x1 : DBYTE */
  44. return MAP_PHY_ADDR(pstate, 10, instance, offset, 0x30);
  45. case 0x2: /* 0x2 : MASTER */
  46. return MAP_PHY_ADDR(pstate, 1, 0, offset, 0x58);
  47. case 0x4: /* 0x4 : ACSM */
  48. return MAP_PHY_ADDR(pstate, 1, 0, offset, 0x5c);
  49. case 0x5: /* 0x5 : μCTL Memory */
  50. return MAP_PHY_ADDR(pstate, 0, instance, offset, 0x60);
  51. case 0x7: /* 0x7 : PPGC */
  52. return MAP_PHY_ADDR(pstate, 0, 0, offset, 0x68);
  53. case 0x9: /* 0x9 : INITENG */
  54. return MAP_PHY_ADDR(pstate, 1, 0, offset, 0x69);
  55. case 0xc: /* 0xC : DRTUB */
  56. return MAP_PHY_ADDR(pstate, 0, 0, offset, 0x6d);
  57. case 0xd: /* 0xD : APB Only */
  58. return MAP_PHY_ADDR(pstate, 0, 0, offset, 0x6e);
  59. default:
  60. printf("ERR: Invalid block_type = 0x%x\n", block_type);
  61. return 0;
  62. }
  63. }
  64. static inline uint16_t *phy_io_addr(void *phy, uint32_t addr)
  65. {
  66. return phy + (map_phy_addr_space(addr) << 2);
  67. }
  68. static inline void phy_io_write16(uint16_t *phy, uint32_t addr, uint16_t data)
  69. {
  70. mmio_write_16((uintptr_t)phy_io_addr(phy, addr), data);
  71. #ifdef DEBUG_PHY_IO
  72. printf("0x%06x,0x%x\n", addr, data);
  73. #endif
  74. }
  75. static inline uint16_t phy_io_read16(uint16_t *phy, uint32_t addr)
  76. {
  77. uint16_t reg = mmio_read_16((uintptr_t) phy_io_addr(phy, addr));
  78. #ifdef DEBUG_PHY_IO
  79. printf("R: 0x%06x,0x%x\n", addr, reg);
  80. #endif
  81. return reg;
  82. }
  83. #ifdef NXP_APPLY_MAX_CDD
  84. #define CDD_VAL_READ_ADDR (0x054012)
  85. #define CDD_DATA_LEN (60)
  86. static void read_phy_reg(uint16_t *phy, uint32_t addr,
  87. uint16_t *buf, uint32_t len)
  88. {
  89. uint32_t i = 0U;
  90. for (i = 0U; i < len/2; i++) {
  91. buf[i] = phy_io_read16(phy, (addr + i));
  92. }
  93. }
  94. static uint32_t findrank(uint32_t cs_in_use)
  95. {
  96. uint32_t val = 0U;
  97. switch (cs_in_use) {
  98. case U(0xf):
  99. val = 4U;
  100. break;
  101. case U(0x3):
  102. val = 2U;
  103. break;
  104. case U(0x1):
  105. val = 1U;
  106. break;
  107. default:
  108. printf("Error - Invalid cs_in_use value\n");
  109. }
  110. return val;
  111. }
  112. static uint8_t findmax(uint8_t *buf, uint32_t len)
  113. {
  114. uint8_t max = 0U;
  115. uint32_t i = 0U;
  116. for (i = 0U; i < len; i++) {
  117. if (buf[i] > max) {
  118. max = buf[i];
  119. }
  120. }
  121. return max;
  122. }
  123. static void get_cdd_val(uint16_t **phy_ptr, uint32_t rank, uint32_t freq,
  124. uint32_t *tcfg0, uint32_t *tcfg4)
  125. {
  126. uint8_t cdd[CDD_DATA_LEN+4] = {0U};
  127. uint32_t i, val = 0U;
  128. uint16_t *phy;
  129. uint8_t buf[16] = {U(0x0)};
  130. uint8_t trr = 0U, tww = 0U, trw = 0U, twr = 0U;
  131. uint8_t rrmax = 0U, wwmax = 0U, rwmax = 0U, wrmax = 0U;
  132. uint8_t tmp = U(0x0);
  133. uint8_t *c = NULL;
  134. for (i = 0U; i < NUM_OF_DDRC; i++) {
  135. phy = phy_ptr[i];
  136. if (phy == NULL) {
  137. continue;
  138. }
  139. phy_io_write16(phy, t_apbonly |
  140. csr_micro_cont_mux_sel_addr, U(0x0));
  141. read_phy_reg(phy, CDD_VAL_READ_ADDR,
  142. (uint16_t *)&cdd, CDD_DATA_LEN);
  143. phy_io_write16(phy, t_apbonly |
  144. csr_micro_cont_mux_sel_addr, U(0x1));
  145. /* CDD values and address
  146. *
  147. * 0x054012 0x24 cdd[0] CDD[X][X]
  148. * 0x054012 0x25 cdd[1] RR[3][2]
  149. * 0x054013 0x26 cdd[2] RR[3][1]
  150. * 0x054013 0x27 cdd[3] RR[3][0]
  151. * 0x054014 0x28 cdd[4] RR[2][3]
  152. * 0x054014 0x29 cdd[5] RR[2][1]
  153. * 0x054015 0x2a cdd[6] RR[2][0]
  154. * 0x054015 0x2b cdd[7] RR[1][3]
  155. * 0x054016 0x2c cdd[8] RR[1][2]
  156. * 0x054016 0x2d cdd[9] RR[1][0]
  157. * 0x054017 0x2e cdd[10] RR[0][3]
  158. * 0x054017 0x2f cdd[11] RR[0][2]
  159. * 0x054018 0x30 cdd[12] RR[0][1]
  160. * 0x054018 0x31 cdd[13] WW[3][2]
  161. * 0x054019 0x32 cdd[14] WW[3][1]
  162. * 0x054019 0x33 cdd[15] WW[3][0]
  163. * 0x05401a 0x34 cdd[16] WW[2][3]
  164. * 0x05401a 0x35 cdd[17] WW[2][1]
  165. * 0x05401b 0x36 cdd[18] WW[2][0]
  166. * 0x05401b 0x37 cdd[19] WW[1][3]
  167. * 0x05401c 0x38 cdd[20] WW[1][2]
  168. * 0x05401c 0x39 cdd[21] WW[1][0]
  169. * 0x05401d 0x3a cdd[22] WW[0][3]
  170. * 0x05401d 0x3b cdd[23] WW[0][2]
  171. * 0x05401e 0x3c cdd[24] WW[0][1]
  172. * 0x05401e 0x3d cdd[25] RW[3][3]
  173. * 0x05401f 0x3e cdd[26] RW[3][2]
  174. * 0x05401f 0x3f cdd[27] RW[3][1]
  175. * 0x054020 0x40 cdd[28] RW[3][0]
  176. * 0x054020 0x41 cdd[29] RW[2][3]
  177. * 0x054021 0x42 cdd[30] RW[2][2]
  178. * 0x054021 0x43 cdd[31] RW[2][1]
  179. * 0x054022 0x44 cdd[32] RW[2][0]
  180. * 0x054022 0x45 cdd[33] RW[1][3]
  181. * 0x054023 0x46 cdd[34] RW[1][2]
  182. * 0x054023 0x47 cdd[35] RW[1][1]
  183. * 0x054024 0x48 cdd[36] RW[1][0]
  184. * 0x054024 0x49 cdd[37] RW[0][3]
  185. * 0x054025 0x4a cdd[38] RW[0][2]
  186. * 0x054025 0x4b cdd[39] RW[0][1]
  187. * 0x054026 0x4c cdd[40] RW[0][0]
  188. * 0x054026 0x4d cdd[41] WR[3][3]
  189. * 0x054027 0x4e cdd[42] WR[3][2]
  190. * 0x054027 0x4f cdd[43] WR[3][1]
  191. * 0x054028 0x50 cdd[44] WR[3][0]
  192. * 0x054028 0x51 cdd[45] WR[2][3]
  193. * 0x054029 0x52 cdd[46] WR[2][2]
  194. * 0x054029 0x53 cdd[47] WR[2][1]
  195. * 0x05402a 0x54 cdd[48] WR[2][0]
  196. * 0x05402a 0x55 cdd[49] WR[1][3]
  197. * 0x05402b 0x56 cdd[50] WR[1][2]
  198. * 0x05402b 0x57 cdd[51] WR[1][1]
  199. * 0x05402c 0x58 cdd[52] WR[1][0]
  200. * 0x05402c 0x59 cdd[53] WR[0][3]
  201. * 0x05402d 0x5a cdd[54] WR[0][2]
  202. * 0x05402d 0x5b cdd[55] WR[0][1]
  203. * 0x05402e 0x5c cdd[56] WR[0][0]
  204. * 0x05402e 0x5d cdd[57] CDD[Y][Y]
  205. */
  206. switch (rank) {
  207. case 1U:
  208. tmp = rwmax;
  209. rwmax = cdd[40];
  210. if (tmp > rwmax) {
  211. rwmax = tmp;
  212. }
  213. break;
  214. case 2U:
  215. buf[0] = cdd[12];
  216. buf[1] = cdd[9];
  217. tmp = rrmax;
  218. rrmax = findmax(buf, 2U);
  219. if (tmp > rrmax) {
  220. rrmax = tmp;
  221. }
  222. buf[0] = cdd[24];
  223. buf[1] = cdd[21];
  224. tmp = wwmax;
  225. wwmax = findmax(buf, 2U);
  226. if (tmp > wwmax) {
  227. wwmax = tmp;
  228. }
  229. buf[0] = cdd[40];
  230. buf[1] = cdd[39];
  231. buf[2] = cdd[36];
  232. buf[3] = cdd[35];
  233. tmp = rwmax;
  234. rwmax = findmax(buf, 4U);
  235. if (tmp > rwmax) {
  236. rwmax = tmp;
  237. }
  238. wrmax = wwmax;
  239. break;
  240. case 4U:
  241. tmp = rrmax;
  242. c = &cdd[1];
  243. rrmax = findmax(c, 12U);
  244. if (tmp > rrmax) {
  245. rrmax = tmp;
  246. }
  247. tmp = wwmax;
  248. c = &cdd[13];
  249. wwmax = findmax(c, 12U);
  250. if (tmp > wwmax) {
  251. wwmax = tmp;
  252. }
  253. tmp = rwmax;
  254. c = &cdd[25];
  255. rwmax = findmax(c, 16U);
  256. if (tmp > rwmax) {
  257. rwmax = tmp;
  258. }
  259. wrmax = wwmax;
  260. break;
  261. }
  262. }
  263. rrmax += 3U;
  264. wwmax += 4U;
  265. if (wwmax > 7U) {
  266. wwmax = 7U;
  267. }
  268. if (rrmax > 7U) {
  269. rrmax = 7U;
  270. }
  271. if (wrmax > U(0xf)) {
  272. wrmax = 0U;
  273. }
  274. if (rwmax > U(0x7)) {
  275. rwmax = U(0x7);
  276. }
  277. val = *tcfg0;
  278. tww = (val >> 24U) & U(0x3);
  279. trr = (val >> 26U) & U(0x3);
  280. twr = (val >> 28U) & U(0x3);
  281. trw = (val >> 30U) & U(0x3);
  282. val = *tcfg4;
  283. tww = tww | (((val >> 8U) & U(0x1)) << 2U);
  284. trr = trr | (((val >> 10U) & U(0x1)) << 2U);
  285. twr = twr | (((val >> 12U) & U(0x1)) << 2U);
  286. trw = trw | (((val >> 14U) & U(0x3)) << 2U);
  287. if (trr > rrmax) {
  288. rrmax = trr;
  289. }
  290. if (tww > wwmax) {
  291. wwmax = tww;
  292. }
  293. if (trw > rwmax) {
  294. rwmax = trw;
  295. }
  296. if (twr > wrmax) {
  297. wrmax = twr;
  298. }
  299. debug("CDD rrmax %x wwmax %x rwmax %x wrmax %x\n",
  300. rrmax, wwmax, rwmax, wrmax);
  301. val = ((wwmax & U(0x3)) << 24U)
  302. | ((rrmax & U(0x3)) << 26U)
  303. | ((wrmax & U(0x3)) << 28U)
  304. | ((rwmax & U(0x3)) << 30U);
  305. *tcfg0 = (*tcfg0 & U(0x00FFFFFF)) | (val);
  306. val = (((wwmax >> 2U) & U(0x1)) << 8U)
  307. | (((rrmax >> 2U) & U(0x1)) << 10U)
  308. | (((wrmax >> 2U) & U(0x1)) << 12U)
  309. | (((rwmax >> 2U) & U(0x3)) << 14U);
  310. *tcfg4 = (*tcfg4 & U(0xffff00ff)) | val;
  311. }
  312. #endif
  313. #ifdef NXP_WARM_BOOT
  314. int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
  315. uint32_t num_of_phy, int train2d
  316. #ifdef NXP_APPLY_MAX_CDD
  317. , struct ddr_ctrl_reg_values *ddrctrl_regs
  318. #endif
  319. )
  320. {
  321. uint16_t *phy = NULL, value = 0x0;
  322. uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U;
  323. int i = 0, j = 0, ret = -EINVAL;
  324. ret = xspi_sector_erase(address_to_store, PHY_ERASE_SIZE);
  325. if (ret != 0) {
  326. return -EINVAL;
  327. }
  328. for (j = 0; j < num_of_phy; j++) {
  329. /* Save training values of all PHYs */
  330. phy = phy_ptr[j];
  331. size = sizeof(training_1D_values);
  332. num_of_regs = ARRAY_SIZE(training_1D_values);
  333. /* Enable access to the internal CSRs */
  334. phy_io_write16(phy, t_apbonly |
  335. csr_micro_cont_mux_sel_addr, 0x0);
  336. /* Enable clocks in case they were disabled. */
  337. phy_io_write16(phy, t_drtub |
  338. csr_ucclk_hclk_enables_addr, 0x3);
  339. if (train2d != 0) {
  340. /* Address to store training values is
  341. * to be appended for next PHY
  342. */
  343. phy_store = address_to_store + (j *
  344. (sizeof(training_1D_values) +
  345. sizeof(training_2D_values)));
  346. } else {
  347. phy_store = address_to_store + (j *
  348. (sizeof(training_1D_values)));
  349. }
  350. debug("Saving 1D Training reg val at: %d\n", phy_store);
  351. for (i = 0; i < num_of_regs; i++) {
  352. value = phy_io_read16(phy, training_1D_values[i].addr);
  353. #ifdef DEBUG_WARM_RESET
  354. debug("%d. Reg: %x, value: %x PHY: %p\n", i,
  355. training_1D_values[i].addr, value,
  356. phy_io_addr(phy,
  357. training_1D_values[i].addr));
  358. #endif
  359. training_1D_values[i].data = value;
  360. }
  361. /* Storing 1D training values on flash */
  362. ret = xspi_write(phy_store, (void *)training_1D_values, size);
  363. if (train2d != 0) {
  364. phy_store = phy_store+size;
  365. size = sizeof(training_2D_values);
  366. num_of_regs = ARRAY_SIZE(training_2D_values);
  367. debug("Saving 2D Training reg val at:%d\n", phy_store);
  368. for (i = 0; i < num_of_regs; i++) {
  369. value = phy_io_read16(phy,
  370. training_2D_values[i].addr);
  371. training_2D_values[i].data = value;
  372. #ifdef DEBUG_WARM_RESET
  373. debug("%d.2D addr:0x%x,val:0x%x,PHY:0x%p\n",
  374. i, training_2D_values[i].addr,
  375. value, phy_io_addr(phy,
  376. training_2D_values[i].addr));
  377. #endif
  378. }
  379. /* Storing 2D training values on flash */
  380. ret = xspi_write(phy_store, training_2D_values,
  381. size);
  382. }
  383. #ifdef NXP_APPLY_MAX_CDD
  384. /* Save DDR control register Timing CFG 0 and 4 */
  385. phy_store += size;
  386. size = sizeof(ddrctrl_regs);
  387. if (ret != 0) {
  388. ret = xspi_write(phy_store, ddrctrl_regs, size);
  389. }
  390. #endif
  391. /* Disable clocks in case they were disabled. */
  392. phy_io_write16(phy, t_drtub |
  393. csr_ucclk_hclk_enables_addr, 0x0);
  394. /* Disable access to the internal CSRs */
  395. phy_io_write16(phy, t_apbonly |
  396. csr_micro_cont_mux_sel_addr, 0x1);
  397. }
  398. if (ret != 0) {
  399. return -EINVAL;
  400. }
  401. return 0;
  402. }
  403. int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
  404. uint32_t num_of_phy, int train2d
  405. #ifdef NXP_APPLY_MAX_CDD
  406. , struct ddr_ctrl_reg_values *ddrctrl_regs
  407. #endif
  408. )
  409. {
  410. uint16_t *phy = NULL;
  411. uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U;
  412. int i = 0, j = 0, ret = -EINVAL;
  413. debug("Restoring Training register values\n");
  414. for (j = 0; j < num_of_phy; j++) {
  415. phy = phy_ptr[j];
  416. size = sizeof(training_1D_values);
  417. num_of_regs = ARRAY_SIZE(training_1D_values);
  418. if (train2d != 0) {
  419. /* The address to restore training values is
  420. * to be appended for next PHY
  421. */
  422. phy_store = address_to_restore + (j *
  423. (sizeof(training_1D_values) +
  424. sizeof(training_2D_values)));
  425. } else {
  426. phy_store = address_to_restore + (j *
  427. (sizeof(training_1D_values)));
  428. }
  429. /* Enable access to the internal CSRs */
  430. phy_io_write16(phy, t_apbonly |
  431. csr_micro_cont_mux_sel_addr, 0x0);
  432. /* Enable clocks in case they were disabled. */
  433. phy_io_write16(phy, t_drtub |
  434. csr_ucclk_hclk_enables_addr, 0x3);
  435. /* Reading 1D training values from flash*/
  436. ret = xspi_read(phy_store, (uint32_t *)training_1D_values,
  437. size);
  438. if (ret != 0) {
  439. #ifdef DEBUG_WARM_RESET
  440. debug("Unable to Read 1D training values %d\n",
  441. ret);
  442. #endif
  443. return -EINVAL;
  444. }
  445. debug("Restoring 1D Training reg val at:%08x\n", phy_store);
  446. for (i = 0; i < num_of_regs; i++) {
  447. phy_io_write16(phy, training_1D_values[i].addr,
  448. training_1D_values[i].data);
  449. #ifdef DEBUG_WARM_RESET
  450. debug("%d. Reg: %x, value: %x PHY: %p\n", i,
  451. training_1D_values[i].addr,
  452. training_1D_values[i].data,
  453. phy_io_addr(phy,
  454. training_1D_values[i].addr));
  455. #endif
  456. }
  457. if (train2d != 0) {
  458. phy_store = phy_store + size;
  459. size = sizeof(training_2D_values);
  460. num_of_regs = ARRAY_SIZE(training_2D_values);
  461. /* Reading 2D training values from flash */
  462. ret = xspi_read(phy_store,
  463. (uint32_t *)training_2D_values, size);
  464. if (ret != 0) {
  465. #ifdef DEBUG_WARM_RESET
  466. debug("Unable to Read 2D training values %d\n",
  467. ret);
  468. #endif
  469. return -EINVAL;
  470. }
  471. debug("Restoring 2D Training reg val at:%08x\n",
  472. phy_store);
  473. for (i = 0; i < num_of_regs; i++) {
  474. phy_io_write16(phy, training_2D_values[i].addr,
  475. training_2D_values[i].data);
  476. #ifdef DEBUG_WARM_RESET
  477. debug("%d. Reg: %x, value: %x PHY: %p\n", i,
  478. training_2D_values[i].addr,
  479. training_2D_values[i].data,
  480. phy_io_addr(phy,
  481. training_1D_values[i].addr));
  482. #endif
  483. }
  484. }
  485. #ifdef NXP_APPLY_MAX_CDD
  486. phy_store = phy_store + size;
  487. size = sizeof(ddrctrl_regs);
  488. ret = xspi_read(phy_store, (uint32_t *)ddrctrl_regs, size);
  489. #endif
  490. /* Disable clocks in case they were disabled. */
  491. phy_io_write16(phy, t_drtub |
  492. csr_ucclk_hclk_enables_addr, 0x0);
  493. /* Disable access to the internal CSRs */
  494. phy_io_write16(phy, t_apbonly |
  495. csr_micro_cont_mux_sel_addr, 0x1);
  496. }
  497. if (ret != 0) {
  498. return -EINVAL;
  499. }
  500. return 0;
  501. }
  502. #endif
  503. static void load_pieimage(uint16_t *phy,
  504. enum dimm_types dimm_type)
  505. {
  506. int i;
  507. int size;
  508. const struct pie *image = NULL;
  509. switch (dimm_type) {
  510. case UDIMM:
  511. case SODIMM:
  512. case NODIMM:
  513. image = pie_udimm;
  514. size = ARRAY_SIZE(pie_udimm);
  515. break;
  516. case RDIMM:
  517. image = pie_rdimm;
  518. size = ARRAY_SIZE(pie_rdimm);
  519. break;
  520. case LRDIMM:
  521. image = pie_lrdimm;
  522. size = ARRAY_SIZE(pie_lrdimm);
  523. break;
  524. default:
  525. printf("Unsupported DIMM type\n");
  526. break;
  527. }
  528. if (image != NULL) {
  529. for (i = 0; i < size; i++)
  530. phy_io_write16(phy, image[i].addr, image[i].data);
  531. }
  532. }
  533. static void prog_acsm_playback(uint16_t *phy,
  534. const struct input *input, const void *msg)
  535. {
  536. int vec;
  537. const struct ddr4r1d *msg_blk;
  538. uint16_t acsmplayback[2][3];
  539. uint32_t f0rc0a;
  540. uint32_t f0rc3x;
  541. uint32_t f0rc5x;
  542. if (input->basic.dimm_type != RDIMM) {
  543. return;
  544. }
  545. msg_blk = msg;
  546. f0rc0a = (msg_blk->f0rc0a_d0 & U(0xf)) | U(0xa0);
  547. f0rc3x = (msg_blk->f0rc3x_d0 & U(0xff)) | U(0x300);
  548. f0rc5x = (input->adv.phy_gen2_umctl_f0rc5x & U(0xff)) | U(0x500);
  549. acsmplayback[0][0] = U(0x3ff) & f0rc0a;
  550. acsmplayback[1][0] = (U(0x1c00) & f0rc0a) >> 10U;
  551. acsmplayback[0][1] = U(0x3ff) & f0rc3x;
  552. acsmplayback[1][1] = (U(0x1c00) & f0rc3x) >> 10U;
  553. acsmplayback[0][2] = U(0x3ff) & f0rc5x;
  554. acsmplayback[1][2] = (U(0x1c00) & f0rc5x) >> 10U;
  555. for (vec = 0; vec < 3; vec++) {
  556. phy_io_write16(phy, t_acsm | (csr_acsm_playback0x0_addr +
  557. (vec << 1)), acsmplayback[0][vec]);
  558. phy_io_write16(phy, t_acsm | (csr_acsm_playback1x0_addr +
  559. (vec << 1)), acsmplayback[1][vec]);
  560. }
  561. }
  562. static void prog_acsm_ctr(uint16_t *phy,
  563. const struct input *input)
  564. {
  565. if (input->basic.dimm_type != RDIMM) {
  566. return;
  567. }
  568. phy_io_write16(phy, t_acsm | csr_acsm_ctrl13_addr,
  569. 0xf << csr_acsm_cke_enb_lsb);
  570. phy_io_write16(phy, t_acsm | csr_acsm_ctrl0_addr,
  571. csr_acsm_par_mode_mask | csr_acsm_2t_mode_mask);
  572. }
  573. static void prog_cal_rate_run(uint16_t *phy,
  574. const struct input *input)
  575. {
  576. int cal_rate;
  577. int cal_interval;
  578. int cal_once;
  579. uint32_t addr;
  580. cal_interval = input->adv.cal_interval;
  581. cal_once = input->adv.cal_once;
  582. cal_rate = 0x1 << csr_cal_run_lsb |
  583. cal_once << csr_cal_once_lsb |
  584. cal_interval << csr_cal_interval_lsb;
  585. addr = t_master | csr_cal_rate_addr;
  586. phy_io_write16(phy, addr, cal_rate);
  587. }
  588. static void prog_seq0bdly0(uint16_t *phy,
  589. const struct input *input)
  590. {
  591. int ps_count[4];
  592. int frq;
  593. uint32_t addr;
  594. int lower_freq_opt = 0;
  595. __unused const soc_info_t *soc_info;
  596. frq = input->basic.frequency >> 1;
  597. ps_count[0] = frq >> 3; /* 0.5 * frq / 4*/
  598. if (input->basic.frequency < 400) {
  599. lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 7 : 3;
  600. } else if (input->basic.frequency < 533) {
  601. lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 14 : 11;
  602. }
  603. /* 1.0 * frq / 4 - lower_freq */
  604. ps_count[1] = (frq >> 2) - lower_freq_opt;
  605. ps_count[2] = (frq << 1) + (frq >> 1); /* 10.0 * frq / 4 */
  606. #ifdef DDR_PLL_FIX
  607. soc_info = get_soc_info();
  608. if (soc_info->svr_reg.bf.maj_ver == 1) {
  609. ps_count[0] = 0x520; /* seq0bdly0 */
  610. ps_count[1] = 0xa41; /* seq0bdly1 */
  611. ps_count[2] = 0x668a; /* seq0bdly2 */
  612. }
  613. #endif
  614. if (frq > 266) {
  615. ps_count[3] = 44;
  616. } else if (frq > 200) {
  617. ps_count[3] = 33;
  618. } else {
  619. ps_count[3] = 16;
  620. }
  621. addr = t_master | csr_seq0bdly0_addr;
  622. phy_io_write16(phy, addr, ps_count[0]);
  623. debug("seq0bdly0 = 0x%x\n", phy_io_read16(phy, addr));
  624. addr = t_master | csr_seq0bdly1_addr;
  625. phy_io_write16(phy, addr, ps_count[1]);
  626. debug("seq0bdly1 = 0x%x\n", phy_io_read16(phy, addr));
  627. addr = t_master | csr_seq0bdly2_addr;
  628. phy_io_write16(phy, addr, ps_count[2]);
  629. debug("seq0bdly2 = 0x%x\n", phy_io_read16(phy, addr));
  630. addr = t_master | csr_seq0bdly3_addr;
  631. phy_io_write16(phy, addr, ps_count[3]);
  632. debug("seq0bdly3 = 0x%x\n", phy_io_read16(phy, addr));
  633. }
  634. /* Only RDIMM requires msg_blk */
  635. static void i_load_pie(uint16_t **phy_ptr,
  636. const struct input *input,
  637. const void *msg)
  638. {
  639. int i;
  640. uint16_t *phy;
  641. for (i = 0; i < NUM_OF_DDRC; i++) {
  642. phy = phy_ptr[i];
  643. if (phy == NULL) {
  644. continue;
  645. }
  646. phy_io_write16(phy,
  647. t_apbonly | csr_micro_cont_mux_sel_addr,
  648. 0U);
  649. load_pieimage(phy, input->basic.dimm_type);
  650. prog_seq0bdly0(phy, input);
  651. phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag0_addr,
  652. U(0x0000));
  653. phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag1_addr,
  654. U(0x0173));
  655. phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag2_addr,
  656. U(0x0060));
  657. phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag3_addr,
  658. U(0x6110));
  659. phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag4_addr,
  660. U(0x2152));
  661. phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag5_addr,
  662. U(0xdfbd));
  663. phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag6_addr,
  664. input->basic.dimm_type == RDIMM &&
  665. input->adv.phy_gen2_umctl_opt == 1U ?
  666. U(0x6000) : U(0xffff));
  667. phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag7_addr,
  668. U(0x6152));
  669. prog_acsm_playback(phy, input, msg); /* rdimm */
  670. prog_acsm_ctr(phy, input); /* rdimm */
  671. phy_io_write16(phy, t_master | csr_cal_zap_addr, U(0x1));
  672. prog_cal_rate_run(phy, input);
  673. phy_io_write16(phy, t_drtub | csr_ucclk_hclk_enables_addr,
  674. input->basic.dimm_type == RDIMM ? U(0x2) : 0U);
  675. phy_io_write16(phy, t_apbonly | csr_micro_cont_mux_sel_addr, 1U);
  676. }
  677. }
  678. static void phy_gen2_init_input(struct input *input)
  679. {
  680. int i;
  681. input->adv.dram_byte_swap = 0;
  682. input->adv.ext_cal_res_val = 0;
  683. input->adv.tx_slew_rise_dq = 0xf;
  684. input->adv.tx_slew_fall_dq = 0xf;
  685. input->adv.tx_slew_rise_ac = 0xf;
  686. input->adv.tx_slew_fall_ac = 0xf;
  687. input->adv.mem_alert_en = 0;
  688. input->adv.mem_alert_puimp = 5;
  689. input->adv.mem_alert_vref_level = 0x29;
  690. input->adv.mem_alert_sync_bypass = 0;
  691. input->adv.cal_interval = 0x9;
  692. input->adv.cal_once = 0;
  693. input->adv.dis_dyn_adr_tri = 0;
  694. input->adv.is2ttiming = 0;
  695. input->adv.d4rx_preamble_length = 0;
  696. input->adv.d4tx_preamble_length = 0;
  697. for (i = 0; i < 7; i++) {
  698. debug("mr[%d] = 0x%x\n", i, input->mr[i]);
  699. }
  700. debug("input->cs_d0 = 0x%x\n", input->cs_d0);
  701. debug("input->cs_d1 = 0x%x\n", input->cs_d1);
  702. debug("input->mirror = 0x%x\n", input->mirror);
  703. debug("PHY ODT impedance = %d ohm\n", input->adv.odtimpedance);
  704. debug("PHY DQ driver impedance = %d ohm\n", input->adv.tx_impedance);
  705. debug("PHY Addr driver impedance = %d ohm\n", input->adv.atx_impedance);
  706. for (i = 0; i < 4; i++) {
  707. debug("odt[%d] = 0x%x\n", i, input->odt[i]);
  708. }
  709. if (input->basic.dimm_type == RDIMM) {
  710. for (i = 0; i < 16; i++) {
  711. debug("input->rcw[%d] = 0x%x\n", i, input->rcw[i]);
  712. }
  713. debug("input->rcw3x = 0x%x\n", input->rcw3x);
  714. }
  715. }
  716. /*
  717. * All protocols share the same base structure of message block.
  718. * RDIMM and LRDIMM have more entries defined than UDIMM.
  719. * Create message blocks for 1D and 2D training.
  720. * Update len with message block size.
  721. */
  722. static int phy_gen2_msg_init(void *msg_1d,
  723. void *msg_2d,
  724. const struct input *input)
  725. {
  726. struct ddr4u1d *msg_blk = msg_1d;
  727. struct ddr4u2d *msg_blk_2d = msg_2d;
  728. struct ddr4r1d *msg_blk_r;
  729. struct ddr4lr1d *msg_blk_lr;
  730. switch (input->basic.dimm_type) {
  731. case UDIMM:
  732. case SODIMM:
  733. case NODIMM:
  734. msg_blk->dram_type = U(0x2);
  735. break;
  736. case RDIMM:
  737. msg_blk->dram_type = U(0x4);
  738. break;
  739. case LRDIMM:
  740. msg_blk->dram_type = U(0x5);
  741. break;
  742. default:
  743. ERROR("Unsupported DIMM type\n");
  744. return -EINVAL;
  745. }
  746. msg_blk->pstate = 0U;
  747. /*Enable quickRd2D, a substage of read deskew, to 1D training.*/
  748. msg_blk->reserved00 = U(0x20);
  749. /*Enable High-Effort WrDQ1D.*/
  750. msg_blk->reserved00 |= U(0x40);
  751. /* Enable 1D extra effort training.*/
  752. msg_blk->reserved1c[3] = U(0x3);
  753. if (input->basic.dimm_type == LRDIMM) {
  754. msg_blk->sequence_ctrl = U(0x3f1f);
  755. } else {
  756. msg_blk->sequence_ctrl = U(0x031f);
  757. }
  758. msg_blk->phy_config_override = 0U;
  759. #ifdef DDR_PHY_DEBUG
  760. msg_blk->hdt_ctrl = U(0x5);
  761. #else
  762. msg_blk->hdt_ctrl = U(0xc9);
  763. #endif
  764. msg_blk->msg_misc = U(0x0);
  765. msg_blk->dfimrlmargin = U(0x1);
  766. msg_blk->phy_vref = input->vref ? input->vref : U(0x61);
  767. msg_blk->cs_present = input->cs_d0 | input->cs_d1;
  768. msg_blk->cs_present_d0 = input->cs_d0;
  769. msg_blk->cs_present_d1 = input->cs_d1;
  770. if (input->mirror != 0) {
  771. msg_blk->addr_mirror = U(0x0a); /* odd CS are mirrored */
  772. }
  773. msg_blk->share2dvref_result = 1U;
  774. msg_blk->acsm_odt_ctrl0 = input->odt[0];
  775. msg_blk->acsm_odt_ctrl1 = input->odt[1];
  776. msg_blk->acsm_odt_ctrl2 = input->odt[2];
  777. msg_blk->acsm_odt_ctrl3 = input->odt[3];
  778. msg_blk->enabled_dqs = (input->basic.num_active_dbyte_dfi0 +
  779. input->basic.num_active_dbyte_dfi1) * 8;
  780. msg_blk->x16present = input->basic.dram_data_width == 0x10 ?
  781. msg_blk->cs_present : 0;
  782. msg_blk->d4misc = U(0x1);
  783. msg_blk->cs_setup_gddec = U(0x1);
  784. msg_blk->rtt_nom_wr_park0 = 0U;
  785. msg_blk->rtt_nom_wr_park1 = 0U;
  786. msg_blk->rtt_nom_wr_park2 = 0U;
  787. msg_blk->rtt_nom_wr_park3 = 0U;
  788. msg_blk->rtt_nom_wr_park4 = 0U;
  789. msg_blk->rtt_nom_wr_park5 = 0U;
  790. msg_blk->rtt_nom_wr_park6 = 0U;
  791. msg_blk->rtt_nom_wr_park7 = 0U;
  792. msg_blk->mr0 = input->mr[0];
  793. msg_blk->mr1 = input->mr[1];
  794. msg_blk->mr2 = input->mr[2];
  795. msg_blk->mr3 = input->mr[3];
  796. msg_blk->mr4 = input->mr[4];
  797. msg_blk->mr5 = input->mr[5];
  798. msg_blk->mr6 = input->mr[6];
  799. if ((msg_blk->mr4 & U(0x1c0)) != 0U) {
  800. ERROR("Setting DRAM CAL mode is not supported\n");
  801. }
  802. msg_blk->alt_cas_l = 0U;
  803. msg_blk->alt_wcas_l = 0U;
  804. msg_blk->dramfreq = input->basic.frequency * 2U;
  805. msg_blk->pll_bypass_en = input->basic.pll_bypass;
  806. msg_blk->dfi_freq_ratio = input->basic.dfi_freq_ratio == 0U ? 1U :
  807. input->basic.dfi_freq_ratio == 1U ? 2U :
  808. 4U;
  809. msg_blk->bpznres_val = input->adv.ext_cal_res_val;
  810. msg_blk->disabled_dbyte = 0U;
  811. debug("msg_blk->dram_type = 0x%x\n", msg_blk->dram_type);
  812. debug("msg_blk->sequence_ctrl = 0x%x\n", msg_blk->sequence_ctrl);
  813. debug("msg_blk->phy_cfg = 0x%x\n", msg_blk->phy_cfg);
  814. debug("msg_blk->x16present = 0x%x\n", msg_blk->x16present);
  815. debug("msg_blk->dramfreq = 0x%x\n", msg_blk->dramfreq);
  816. debug("msg_blk->pll_bypass_en = 0x%x\n", msg_blk->pll_bypass_en);
  817. debug("msg_blk->dfi_freq_ratio = 0x%x\n", msg_blk->dfi_freq_ratio);
  818. debug("msg_blk->phy_odt_impedance = 0x%x\n",
  819. msg_blk->phy_odt_impedance);
  820. debug("msg_blk->phy_drv_impedance = 0x%x\n",
  821. msg_blk->phy_drv_impedance);
  822. debug("msg_blk->bpznres_val = 0x%x\n", msg_blk->bpznres_val);
  823. debug("msg_blk->enabled_dqs = 0x%x\n", msg_blk->enabled_dqs);
  824. debug("msg_blk->acsm_odt_ctrl0 = 0x%x\n", msg_blk->acsm_odt_ctrl0);
  825. debug("msg_blk->acsm_odt_ctrl1 = 0x%x\n", msg_blk->acsm_odt_ctrl1);
  826. debug("msg_blk->acsm_odt_ctrl2 = 0x%x\n", msg_blk->acsm_odt_ctrl2);
  827. debug("msg_blk->acsm_odt_ctrl3 = 0x%x\n", msg_blk->acsm_odt_ctrl3);
  828. /* RDIMM only */
  829. if (input->basic.dimm_type == RDIMM ||
  830. input->basic.dimm_type == LRDIMM) {
  831. msg_blk_r = (struct ddr4r1d *)msg_blk;
  832. if (msg_blk_r->cs_present_d0 != 0U) {
  833. msg_blk_r->f0rc00_d0 = input->rcw[0];
  834. msg_blk_r->f0rc01_d0 = input->rcw[1];
  835. msg_blk_r->f0rc02_d0 = input->rcw[2];
  836. msg_blk_r->f0rc03_d0 = input->rcw[3];
  837. msg_blk_r->f0rc04_d0 = input->rcw[4];
  838. msg_blk_r->f0rc05_d0 = input->rcw[5];
  839. msg_blk_r->f0rc06_d0 = input->rcw[6];
  840. msg_blk_r->f0rc07_d0 = input->rcw[7];
  841. msg_blk_r->f0rc08_d0 = input->rcw[8];
  842. msg_blk_r->f0rc09_d0 = input->rcw[9];
  843. msg_blk_r->f0rc0a_d0 = input->rcw[10];
  844. msg_blk_r->f0rc0b_d0 = input->rcw[11];
  845. msg_blk_r->f0rc0c_d0 = input->rcw[12];
  846. msg_blk_r->f0rc0d_d0 = input->rcw[13];
  847. msg_blk_r->f0rc0e_d0 = input->rcw[14];
  848. msg_blk_r->f0rc0f_d0 = input->rcw[15];
  849. msg_blk_r->f0rc3x_d0 = input->rcw3x;
  850. }
  851. if (msg_blk_r->cs_present_d1 != 0) {
  852. msg_blk_r->f0rc00_d1 = input->rcw[0];
  853. msg_blk_r->f0rc01_d1 = input->rcw[1];
  854. msg_blk_r->f0rc02_d1 = input->rcw[2];
  855. msg_blk_r->f0rc03_d1 = input->rcw[3];
  856. msg_blk_r->f0rc04_d1 = input->rcw[4];
  857. msg_blk_r->f0rc05_d1 = input->rcw[5];
  858. msg_blk_r->f0rc06_d1 = input->rcw[6];
  859. msg_blk_r->f0rc07_d1 = input->rcw[7];
  860. msg_blk_r->f0rc08_d1 = input->rcw[8];
  861. msg_blk_r->f0rc09_d1 = input->rcw[9];
  862. msg_blk_r->f0rc0a_d1 = input->rcw[10];
  863. msg_blk_r->f0rc0b_d1 = input->rcw[11];
  864. msg_blk_r->f0rc0c_d1 = input->rcw[12];
  865. msg_blk_r->f0rc0d_d1 = input->rcw[13];
  866. msg_blk_r->f0rc0e_d1 = input->rcw[14];
  867. msg_blk_r->f0rc0f_d1 = input->rcw[15];
  868. msg_blk_r->f0rc3x_d1 = input->rcw3x;
  869. }
  870. if (input->basic.dimm_type == LRDIMM) {
  871. msg_blk_lr = (struct ddr4lr1d *)msg_blk;
  872. msg_blk_lr->bc0a_d0 = msg_blk_lr->f0rc0a_d0;
  873. msg_blk_lr->bc0a_d1 = msg_blk_lr->f0rc0a_d1;
  874. msg_blk_lr->f0bc6x_d0 = msg_blk_lr->f0rc3x_d0;
  875. msg_blk_lr->f0bc6x_d1 = msg_blk_lr->f0rc3x_d1;
  876. }
  877. }
  878. /* below is different for 1D and 2D message block */
  879. if (input->basic.train2d != 0) {
  880. memcpy(msg_blk_2d, msg_blk, sizeof(struct ddr4u1d));
  881. /*High-Effort WrDQ1D is applicable to 2D traning also*/
  882. msg_blk_2d->reserved00 |= U(0x40);
  883. msg_blk_2d->sequence_ctrl = U(0x0061);
  884. msg_blk_2d->rx2d_train_opt = 0U;
  885. msg_blk_2d->tx2d_train_opt = 0U;
  886. msg_blk_2d->share2dvref_result = 1U;
  887. msg_blk_2d->delay_weight2d = U(0x20);
  888. msg_blk_2d->voltage_weight2d = U(0x80);
  889. debug("rx2d_train_opt %d, tx2d_train_opt %d\n",
  890. msg_blk_2d->rx2d_train_opt,
  891. msg_blk_2d->tx2d_train_opt);
  892. }
  893. msg_blk->phy_cfg = (((msg_blk->mr3 & U(0x8)) != 0U) ||
  894. ((msg_blk_2d->mr3 & 0x8) != 0U)) ? 0U
  895. : input->adv.is2ttiming;
  896. return 0;
  897. }
  898. static void prog_tx_pre_drv_mode(uint16_t *phy,
  899. const struct input *input)
  900. {
  901. int lane, byte, b_addr, c_addr, p_addr;
  902. int tx_slew_rate, tx_pre_p, tx_pre_n;
  903. int tx_pre_drv_mode = 0x2;
  904. uint32_t addr;
  905. /* Program TxPreDrvMode with 0x2 */
  906. /* FIXME: TxPreDrvMode depends on DramType? */
  907. tx_pre_p = input->adv.tx_slew_rise_dq;
  908. tx_pre_n = input->adv.tx_slew_fall_dq;
  909. tx_slew_rate = tx_pre_drv_mode << csr_tx_pre_drv_mode_lsb |
  910. tx_pre_p << csr_tx_pre_p_lsb |
  911. tx_pre_n << csr_tx_pre_n_lsb;
  912. p_addr = 0;
  913. for (byte = 0; byte < input->basic.num_dbyte; byte++) {
  914. c_addr = byte << 12;
  915. for (lane = 0; lane <= 1; lane++) {
  916. b_addr = lane << 8;
  917. addr = p_addr | t_dbyte | c_addr | b_addr |
  918. csr_tx_slew_rate_addr;
  919. phy_io_write16(phy, addr, tx_slew_rate);
  920. }
  921. }
  922. }
  923. static void prog_atx_pre_drv_mode(uint16_t *phy,
  924. const struct input *input)
  925. {
  926. int anib, c_addr;
  927. int atx_slew_rate, atx_pre_p, atx_pre_n, atx_pre_drv_mode,
  928. ck_anib_inst[2];
  929. uint32_t addr;
  930. atx_pre_n = input->adv.tx_slew_fall_ac;
  931. atx_pre_p = input->adv.tx_slew_rise_ac;
  932. if (input->basic.num_anib == 8) {
  933. ck_anib_inst[0] = 1;
  934. ck_anib_inst[1] = 1;
  935. } else if (input->basic.num_anib == 10 || input->basic.num_anib == 12 ||
  936. input->basic.num_anib == 13) {
  937. ck_anib_inst[0] = 4;
  938. ck_anib_inst[1] = 5;
  939. } else {
  940. ERROR("Invalid number of aNIBs: %d\n", input->basic.num_anib);
  941. return;
  942. }
  943. for (anib = 0; anib < input->basic.num_anib; anib++) {
  944. c_addr = anib << 12;
  945. if (anib == ck_anib_inst[0] || anib == ck_anib_inst[1]) {
  946. atx_pre_drv_mode = 0;
  947. } else {
  948. atx_pre_drv_mode = 3;
  949. }
  950. atx_slew_rate = atx_pre_drv_mode << csr_atx_pre_drv_mode_lsb |
  951. atx_pre_n << csr_atx_pre_n_lsb |
  952. atx_pre_p << csr_atx_pre_p_lsb;
  953. addr = t_anib | c_addr | csr_atx_slew_rate_addr;
  954. phy_io_write16(phy, addr, atx_slew_rate);
  955. }
  956. }
  957. static void prog_enable_cs_multicast(uint16_t *phy,
  958. const struct input *input)
  959. {
  960. uint32_t addr = t_master | csr_enable_cs_multicast_addr;
  961. if (input->basic.dimm_type != RDIMM &&
  962. input->basic.dimm_type != LRDIMM) {
  963. return;
  964. }
  965. phy_io_write16(phy, addr, input->adv.cast_cs_to_cid);
  966. }
  967. static void prog_dfi_rd_data_cs_dest_map(uint16_t *phy,
  968. unsigned int ip_rev,
  969. const struct input *input,
  970. const struct ddr4lr1d *msg)
  971. {
  972. const struct ddr4lr1d *msg_blk;
  973. uint16_t dfi_xxdestm0 = 0U;
  974. uint16_t dfi_xxdestm1 = 0U;
  975. uint16_t dfi_xxdestm2 = 0U;
  976. uint16_t dfi_xxdestm3 = 0U;
  977. uint16_t dfi_rd_data_cs_dest_map;
  978. uint16_t dfi_wr_data_cs_dest_map;
  979. __unused const soc_info_t *soc_info;
  980. #ifdef ERRATA_DDR_A011396
  981. /* Only apply to DDRC 5.05.00 */
  982. soc_info = get_soc_info();
  983. if ((soc_info->svr_reg.bf.maj_ver == 1U) && (ip_rev == U(0x50500))) {
  984. phy_io_write16(phy,
  985. t_master | csr_dfi_rd_data_cs_dest_map_addr,
  986. 0U);
  987. return;
  988. }
  989. #endif
  990. msg_blk = msg;
  991. switch (input->basic.dimm_type) {
  992. case UDIMM:
  993. case SODIMM:
  994. case NODIMM:
  995. if ((msg_blk->msg_misc & U(0x40)) != 0U) {
  996. dfi_rd_data_cs_dest_map = U(0xa0);
  997. dfi_wr_data_cs_dest_map = U(0xa0);
  998. phy_io_write16(phy,
  999. t_master | csr_dfi_rd_data_cs_dest_map_addr,
  1000. dfi_rd_data_cs_dest_map);
  1001. phy_io_write16(phy,
  1002. t_master | csr_dfi_wr_data_cs_dest_map_addr,
  1003. dfi_wr_data_cs_dest_map);
  1004. }
  1005. break;
  1006. case LRDIMM:
  1007. if (msg->cs_present_d1 != 0U) {
  1008. dfi_xxdestm2 = 1U;
  1009. dfi_xxdestm3 = 1U;
  1010. }
  1011. dfi_rd_data_cs_dest_map =
  1012. dfi_xxdestm0 << csr_dfi_rd_destm0_lsb |
  1013. dfi_xxdestm1 << csr_dfi_rd_destm1_lsb |
  1014. dfi_xxdestm2 << csr_dfi_rd_destm2_lsb |
  1015. dfi_xxdestm3 << csr_dfi_rd_destm3_lsb;
  1016. dfi_wr_data_cs_dest_map =
  1017. dfi_xxdestm0 << csr_dfi_wr_destm0_lsb |
  1018. dfi_xxdestm1 << csr_dfi_wr_destm1_lsb |
  1019. dfi_xxdestm2 << csr_dfi_wr_destm2_lsb |
  1020. dfi_xxdestm3 << csr_dfi_wr_destm3_lsb;
  1021. phy_io_write16(phy, t_master | csr_dfi_rd_data_cs_dest_map_addr,
  1022. dfi_rd_data_cs_dest_map);
  1023. phy_io_write16(phy, t_master | csr_dfi_wr_data_cs_dest_map_addr,
  1024. dfi_wr_data_cs_dest_map);
  1025. break;
  1026. default:
  1027. break;
  1028. }
  1029. }
  1030. static void prog_pll_ctrl(uint16_t *phy,
  1031. const struct input *input)
  1032. {
  1033. uint32_t addr;
  1034. int pll_ctrl1 = 0x21; /* 000100001b */
  1035. int pll_ctrl4 = 0x17f; /* 101111111b */
  1036. int pll_test_mode = 0x24; /* 00100100b */
  1037. addr = t_master | csr_pll_ctrl1_addr;
  1038. phy_io_write16(phy, addr, pll_ctrl1);
  1039. debug("pll_ctrl1 = 0x%x\n", phy_io_read16(phy, addr));
  1040. addr = t_master | csr_pll_test_mode_addr;
  1041. phy_io_write16(phy, addr, pll_test_mode);
  1042. debug("pll_test_mode = 0x%x\n", phy_io_read16(phy, addr));
  1043. addr = t_master | csr_pll_ctrl4_addr;
  1044. phy_io_write16(phy, addr, pll_ctrl4);
  1045. debug("pll_ctrl4 = 0x%x\n", phy_io_read16(phy, addr));
  1046. }
  1047. static void prog_pll_ctrl2(uint16_t *phy,
  1048. const struct input *input)
  1049. {
  1050. int pll_ctrl2;
  1051. uint32_t addr = t_master | csr_pll_ctrl2_addr;
  1052. if (input->basic.frequency / 2 < 235) {
  1053. pll_ctrl2 = 0x7;
  1054. } else if (input->basic.frequency / 2 < 313) {
  1055. pll_ctrl2 = 0x6;
  1056. } else if (input->basic.frequency / 2 < 469) {
  1057. pll_ctrl2 = 0xb;
  1058. } else if (input->basic.frequency / 2 < 625) {
  1059. pll_ctrl2 = 0xa;
  1060. } else if (input->basic.frequency / 2 < 938) {
  1061. pll_ctrl2 = 0x19;
  1062. } else if (input->basic.frequency / 2 < 1067) {
  1063. pll_ctrl2 = 0x18;
  1064. } else {
  1065. pll_ctrl2 = 0x19;
  1066. }
  1067. phy_io_write16(phy, addr, pll_ctrl2);
  1068. debug("pll_ctrl2 = 0x%x\n", phy_io_read16(phy, addr));
  1069. }
  1070. static void prog_dll_lck_param(uint16_t *phy, const struct input *input)
  1071. {
  1072. uint32_t addr = t_master | csr_dll_lockparam_addr;
  1073. phy_io_write16(phy, addr, U(0x212));
  1074. debug("dll_lck_param = 0x%x\n", phy_io_read16(phy, addr));
  1075. }
  1076. static void prog_dll_gain_ctl(uint16_t *phy, const struct input *input)
  1077. {
  1078. uint32_t addr = t_master | csr_dll_gain_ctl_addr;
  1079. phy_io_write16(phy, addr, U(0x61));
  1080. debug("dll_gain_ctl = 0x%x\n", phy_io_read16(phy, addr));
  1081. }
  1082. static void prog_pll_pwr_dn(uint16_t *phy,
  1083. const struct input *input)
  1084. {
  1085. uint32_t addr;
  1086. addr = t_master | csr_pll_pwr_dn_addr;
  1087. phy_io_write16(phy, addr, 0U);
  1088. debug("pll_pwrdn = 0x%x\n", phy_io_read16(phy, addr));
  1089. }
  1090. static void prog_ard_ptr_init_val(uint16_t *phy,
  1091. const struct input *input)
  1092. {
  1093. int ard_ptr_init_val;
  1094. uint32_t addr = t_master | csr_ard_ptr_init_val_addr;
  1095. if (input->basic.frequency >= 933) {
  1096. ard_ptr_init_val = 0x2;
  1097. } else {
  1098. ard_ptr_init_val = 0x1;
  1099. }
  1100. phy_io_write16(phy, addr, ard_ptr_init_val);
  1101. }
  1102. static void prog_dqs_preamble_control(uint16_t *phy,
  1103. const struct input *input)
  1104. {
  1105. int data;
  1106. uint32_t addr = t_master | csr_dqs_preamble_control_addr;
  1107. const int wdqsextension = 0;
  1108. const int lp4sttc_pre_bridge_rx_en = 0;
  1109. const int lp4postamble_ext = 0;
  1110. const int lp4tgl_two_tck_tx_dqs_pre = 0;
  1111. const int position_dfe_init = 2;
  1112. const int dll_rx_preamble_mode = 1;
  1113. int two_tck_tx_dqs_pre = input->adv.d4tx_preamble_length;
  1114. int two_tck_rx_dqs_pre = input->adv.d4rx_preamble_length;
  1115. data = wdqsextension << csr_wdqsextension_lsb |
  1116. lp4sttc_pre_bridge_rx_en << csr_lp4sttc_pre_bridge_rx_en_lsb |
  1117. lp4postamble_ext << csr_lp4postamble_ext_lsb |
  1118. lp4tgl_two_tck_tx_dqs_pre << csr_lp4tgl_two_tck_tx_dqs_pre_lsb |
  1119. position_dfe_init << csr_position_dfe_init_lsb |
  1120. two_tck_tx_dqs_pre << csr_two_tck_tx_dqs_pre_lsb |
  1121. two_tck_rx_dqs_pre << csr_two_tck_rx_dqs_pre_lsb;
  1122. phy_io_write16(phy, addr, data);
  1123. data = dll_rx_preamble_mode << csr_dll_rx_preamble_mode_lsb;
  1124. addr = t_master | csr_dbyte_dll_mode_cntrl_addr;
  1125. phy_io_write16(phy, addr, data);
  1126. }
  1127. static void prog_proc_odt_time_ctl(uint16_t *phy,
  1128. const struct input *input)
  1129. {
  1130. int proc_odt_time_ctl;
  1131. uint32_t addr = t_master | csr_proc_odt_time_ctl_addr;
  1132. if (input->adv.wdqsext != 0) {
  1133. proc_odt_time_ctl = 0x3;
  1134. } else if (input->basic.frequency <= 933) {
  1135. proc_odt_time_ctl = 0xa;
  1136. } else if (input->basic.frequency <= 1200) {
  1137. if (input->adv.d4rx_preamble_length == 1) {
  1138. proc_odt_time_ctl = 0x2;
  1139. } else {
  1140. proc_odt_time_ctl = 0x6;
  1141. }
  1142. } else {
  1143. if (input->adv.d4rx_preamble_length == 1) {
  1144. proc_odt_time_ctl = 0x3;
  1145. } else {
  1146. proc_odt_time_ctl = 0x7;
  1147. }
  1148. }
  1149. phy_io_write16(phy, addr, proc_odt_time_ctl);
  1150. }
  1151. static const struct impedance_mapping map[] = {
  1152. { 29, 0x3f },
  1153. { 31, 0x3e },
  1154. { 33, 0x3b },
  1155. { 36, 0x3a },
  1156. { 39, 0x39 },
  1157. { 42, 0x38 },
  1158. { 46, 0x1b },
  1159. { 51, 0x1a },
  1160. { 57, 0x19 },
  1161. { 64, 0x18 },
  1162. { 74, 0x0b },
  1163. { 88, 0x0a },
  1164. { 108, 0x09 },
  1165. { 140, 0x08 },
  1166. { 200, 0x03 },
  1167. { 360, 0x02 },
  1168. { 481, 0x01 },
  1169. {}
  1170. };
  1171. static int map_impedance(int strength)
  1172. {
  1173. const struct impedance_mapping *tbl = map;
  1174. int val = 0;
  1175. if (strength == 0) {
  1176. return 0;
  1177. }
  1178. while (tbl->ohm != 0U) {
  1179. if (strength < tbl->ohm) {
  1180. val = tbl->code;
  1181. break;
  1182. }
  1183. tbl++;
  1184. }
  1185. return val;
  1186. }
  1187. static int map_odtstren_p(int strength, int hard_macro_ver)
  1188. {
  1189. int val = -1;
  1190. if (hard_macro_ver == 4) {
  1191. if (strength == 0) {
  1192. val = 0;
  1193. } else if (strength == 120) {
  1194. val = 0x8;
  1195. } else if (strength == 60) {
  1196. val = 0x18;
  1197. } else if (strength == 40) {
  1198. val = 0x38;
  1199. } else {
  1200. printf("error: unsupported ODTStrenP %d\n", strength);
  1201. }
  1202. } else {
  1203. val = map_impedance(strength);
  1204. }
  1205. return val;
  1206. }
  1207. static void prog_tx_odt_drv_stren(uint16_t *phy,
  1208. const struct input *input)
  1209. {
  1210. int lane, byte, b_addr, c_addr;
  1211. int tx_odt_drv_stren;
  1212. int odtstren_p, odtstren_n;
  1213. uint32_t addr;
  1214. odtstren_p = map_odtstren_p(input->adv.odtimpedance,
  1215. input->basic.hard_macro_ver);
  1216. if (odtstren_p < 0) {
  1217. return;
  1218. }
  1219. odtstren_n = 0; /* always high-z */
  1220. tx_odt_drv_stren = odtstren_n << csr_odtstren_n_lsb | odtstren_p;
  1221. for (byte = 0; byte < input->basic.num_dbyte; byte++) {
  1222. c_addr = byte << 12;
  1223. for (lane = 0; lane <= 1; lane++) {
  1224. b_addr = lane << 8;
  1225. addr = t_dbyte | c_addr | b_addr |
  1226. csr_tx_odt_drv_stren_addr;
  1227. phy_io_write16(phy, addr, tx_odt_drv_stren);
  1228. }
  1229. }
  1230. }
  1231. static int map_drvstren_fsdq_p(int strength, int hard_macro_ver)
  1232. {
  1233. int val = -1;
  1234. if (hard_macro_ver == 4) {
  1235. if (strength == 0) {
  1236. val = 0x07;
  1237. } else if (strength == 120) {
  1238. val = 0x0F;
  1239. } else if (strength == 60) {
  1240. val = 0x1F;
  1241. } else if (strength == 40) {
  1242. val = 0x3F;
  1243. } else {
  1244. printf("error: unsupported drv_stren_fSDq_p %d\n",
  1245. strength);
  1246. }
  1247. } else {
  1248. val = map_impedance(strength);
  1249. }
  1250. return val;
  1251. }
  1252. static int map_drvstren_fsdq_n(int strength, int hard_macro_ver)
  1253. {
  1254. int val = -1;
  1255. if (hard_macro_ver == 4) {
  1256. if (strength == 0) {
  1257. val = 0x00;
  1258. } else if (strength == 120) {
  1259. val = 0x08;
  1260. } else if (strength == 60) {
  1261. val = 0x18;
  1262. } else if (strength == 40) {
  1263. val = 0x38;
  1264. } else {
  1265. printf("error: unsupported drvStrenFSDqN %d\n",
  1266. strength);
  1267. }
  1268. } else {
  1269. val = map_impedance(strength);
  1270. }
  1271. return val;
  1272. }
  1273. static void prog_tx_impedance_ctrl1(uint16_t *phy,
  1274. const struct input *input)
  1275. {
  1276. int lane, byte, b_addr, c_addr;
  1277. int tx_impedance_ctrl1;
  1278. int drv_stren_fsdq_p, drv_stren_fsdq_n;
  1279. uint32_t addr;
  1280. drv_stren_fsdq_p = map_drvstren_fsdq_p(input->adv.tx_impedance,
  1281. input->basic.hard_macro_ver);
  1282. drv_stren_fsdq_n = map_drvstren_fsdq_n(input->adv.tx_impedance,
  1283. input->basic.hard_macro_ver);
  1284. tx_impedance_ctrl1 = drv_stren_fsdq_n << csr_drv_stren_fsdq_n_lsb |
  1285. drv_stren_fsdq_p << csr_drv_stren_fsdq_p_lsb;
  1286. for (byte = 0; byte < input->basic.num_dbyte; byte++) {
  1287. c_addr = byte << 12;
  1288. for (lane = 0; lane <= 1; lane++) {
  1289. b_addr = lane << 8;
  1290. addr = t_dbyte | c_addr | b_addr |
  1291. csr_tx_impedance_ctrl1_addr;
  1292. phy_io_write16(phy, addr, tx_impedance_ctrl1);
  1293. }
  1294. }
  1295. }
  1296. static int map_adrv_stren_p(int strength, int hard_macro_ver)
  1297. {
  1298. int val = -1;
  1299. if (hard_macro_ver == 4) {
  1300. if (strength == 120) {
  1301. val = 0x1c;
  1302. } else if (strength == 60) {
  1303. val = 0x1d;
  1304. } else if (strength == 40) {
  1305. val = 0x1f;
  1306. } else {
  1307. printf("error: unsupported aDrv_stren_p %d\n",
  1308. strength);
  1309. }
  1310. } else {
  1311. if (strength == 120) {
  1312. val = 0x00;
  1313. } else if (strength == 60) {
  1314. val = 0x01;
  1315. } else if (strength == 40) {
  1316. val = 0x03;
  1317. } else if (strength == 30) {
  1318. val = 0x07;
  1319. } else if (strength == 24) {
  1320. val = 0x0f;
  1321. } else if (strength == 20) {
  1322. val = 0x1f;
  1323. } else {
  1324. printf("error: unsupported aDrv_stren_p %d\n",
  1325. strength);
  1326. }
  1327. }
  1328. return val;
  1329. }
  1330. static int map_adrv_stren_n(int strength, int hard_macro_ver)
  1331. {
  1332. int val = -1;
  1333. if (hard_macro_ver == 4) {
  1334. if (strength == 120) {
  1335. val = 0x00;
  1336. } else if (strength == 60) {
  1337. val = 0x01;
  1338. } else if (strength == 40) {
  1339. val = 0x03;
  1340. } else {
  1341. printf("Error: unsupported ADrvStrenP %d\n", strength);
  1342. }
  1343. } else {
  1344. if (strength == 120) {
  1345. val = 0x00;
  1346. } else if (strength == 60) {
  1347. val = 0x01;
  1348. } else if (strength == 40) {
  1349. val = 0x03;
  1350. } else if (strength == 30) {
  1351. val = 0x07;
  1352. } else if (strength == 24) {
  1353. val = 0x0f;
  1354. } else if (strength == 20) {
  1355. val = 0x1f;
  1356. } else {
  1357. printf("Error: unsupported ADrvStrenP %d\n", strength);
  1358. }
  1359. }
  1360. return val;
  1361. }
  1362. static void prog_atx_impedance(uint16_t *phy,
  1363. const struct input *input)
  1364. {
  1365. int anib, c_addr;
  1366. int atx_impedance;
  1367. int adrv_stren_p;
  1368. int adrv_stren_n;
  1369. uint32_t addr;
  1370. if (input->basic.hard_macro_ver == 4 &&
  1371. input->adv.atx_impedance == 20) {
  1372. printf("Error:ATxImpedance has to be 40 for HardMacroVer 4\n");
  1373. return;
  1374. }
  1375. adrv_stren_p = map_adrv_stren_p(input->adv.atx_impedance,
  1376. input->basic.hard_macro_ver);
  1377. adrv_stren_n = map_adrv_stren_n(input->adv.atx_impedance,
  1378. input->basic.hard_macro_ver);
  1379. atx_impedance = adrv_stren_n << csr_adrv_stren_n_lsb |
  1380. adrv_stren_p << csr_adrv_stren_p_lsb;
  1381. for (anib = 0; anib < input->basic.num_anib; anib++) {
  1382. c_addr = anib << 12;
  1383. addr = t_anib | c_addr | csr_atx_impedance_addr;
  1384. phy_io_write16(phy, addr, atx_impedance);
  1385. }
  1386. }
  1387. static void prog_dfi_mode(uint16_t *phy,
  1388. const struct input *input)
  1389. {
  1390. int dfi_mode;
  1391. uint32_t addr;
  1392. if (input->basic.dfi1exists == 1) {
  1393. dfi_mode = 0x5; /* DFI1 exists but disabled */
  1394. } else {
  1395. dfi_mode = 0x1; /* DFI1 does not physically exists */
  1396. }
  1397. addr = t_master | csr_dfi_mode_addr;
  1398. phy_io_write16(phy, addr, dfi_mode);
  1399. }
  1400. static void prog_acx4_anib_dis(uint16_t *phy, const struct input *input)
  1401. {
  1402. uint32_t addr;
  1403. addr = t_master | csr_acx4_anib_dis_addr;
  1404. phy_io_write16(phy, addr, 0x0);
  1405. debug("%s 0x%x\n", __func__, phy_io_read16(phy, addr));
  1406. }
  1407. static void prog_dfi_camode(uint16_t *phy,
  1408. const struct input *input)
  1409. {
  1410. int dfi_camode = 2;
  1411. uint32_t addr = t_master | csr_dfi_camode_addr;
  1412. phy_io_write16(phy, addr, dfi_camode);
  1413. }
  1414. static void prog_cal_drv_str0(uint16_t *phy,
  1415. const struct input *input)
  1416. {
  1417. int cal_drv_str0;
  1418. int cal_drv_str_pd50;
  1419. int cal_drv_str_pu50;
  1420. uint32_t addr;
  1421. cal_drv_str_pu50 = input->adv.ext_cal_res_val;
  1422. cal_drv_str_pd50 = cal_drv_str_pu50;
  1423. cal_drv_str0 = cal_drv_str_pu50 << csr_cal_drv_str_pu50_lsb |
  1424. cal_drv_str_pd50;
  1425. addr = t_master | csr_cal_drv_str0_addr;
  1426. phy_io_write16(phy, addr, cal_drv_str0);
  1427. }
  1428. static void prog_cal_uclk_info(uint16_t *phy,
  1429. const struct input *input)
  1430. {
  1431. int cal_uclk_ticks_per1u_s;
  1432. uint32_t addr;
  1433. cal_uclk_ticks_per1u_s = input->basic.frequency >> 1;
  1434. if (cal_uclk_ticks_per1u_s < 24) {
  1435. cal_uclk_ticks_per1u_s = 24;
  1436. }
  1437. addr = t_master | csr_cal_uclk_info_addr;
  1438. phy_io_write16(phy, addr, cal_uclk_ticks_per1u_s);
  1439. }
  1440. static void prog_cal_rate(uint16_t *phy,
  1441. const struct input *input)
  1442. {
  1443. int cal_rate;
  1444. int cal_interval;
  1445. int cal_once;
  1446. uint32_t addr;
  1447. cal_interval = input->adv.cal_interval;
  1448. cal_once = input->adv.cal_once;
  1449. cal_rate = cal_once << csr_cal_once_lsb |
  1450. cal_interval << csr_cal_interval_lsb;
  1451. addr = t_master | csr_cal_rate_addr;
  1452. phy_io_write16(phy, addr, cal_rate);
  1453. }
  1454. static void prog_vref_in_global(uint16_t *phy,
  1455. const struct input *input,
  1456. const struct ddr4u1d *msg)
  1457. {
  1458. int vref_in_global;
  1459. int global_vref_in_dac = 0;
  1460. int global_vref_in_sel = 0;
  1461. uint32_t addr;
  1462. /*
  1463. * phy_vref_prcnt = msg->phy_vref / 128.0
  1464. * global_vref_in_dac = (phy_vref_prcnt - 0.345) / 0.005;
  1465. */
  1466. global_vref_in_dac = (msg->phy_vref * 1000 - 345 * 128 + 320) /
  1467. (5 * 128);
  1468. vref_in_global = global_vref_in_dac << csr_global_vref_in_dac_lsb |
  1469. global_vref_in_sel;
  1470. addr = t_master | csr_vref_in_global_addr;
  1471. phy_io_write16(phy, addr, vref_in_global);
  1472. }
  1473. static void prog_dq_dqs_rcv_cntrl(uint16_t *phy,
  1474. const struct input *input)
  1475. {
  1476. int lane, byte, b_addr, c_addr;
  1477. int dq_dqs_rcv_cntrl;
  1478. int gain_curr_adj_defval = 0xb;
  1479. int major_mode_dbyte = 3;
  1480. int dfe_ctrl_defval = 0;
  1481. int ext_vref_range_defval = 0;
  1482. int sel_analog_vref = 1;
  1483. uint32_t addr;
  1484. #ifdef ERRATA_DDR_A050958
  1485. gain_curr_adj_defval = 0x1f;
  1486. #endif
  1487. dq_dqs_rcv_cntrl = gain_curr_adj_defval << csr_gain_curr_adj_lsb |
  1488. major_mode_dbyte << csr_major_mode_dbyte_lsb |
  1489. dfe_ctrl_defval << csr_dfe_ctrl_lsb |
  1490. ext_vref_range_defval << csr_ext_vref_range_lsb |
  1491. sel_analog_vref << csr_sel_analog_vref_lsb;
  1492. for (byte = 0; byte < input->basic.num_dbyte; byte++) {
  1493. c_addr = byte << 12;
  1494. for (lane = 0; lane <= 1; lane++) {
  1495. b_addr = lane << 8;
  1496. addr = t_dbyte | c_addr | b_addr |
  1497. csr_dq_dqs_rcv_cntrl_addr;
  1498. phy_io_write16(phy, addr, dq_dqs_rcv_cntrl);
  1499. }
  1500. }
  1501. }
  1502. static void prog_mem_alert_control(uint16_t *phy,
  1503. const struct input *input)
  1504. {
  1505. int mem_alert_control;
  1506. int mem_alert_control2;
  1507. int malertpu_en;
  1508. int malertrx_en;
  1509. int malertvref_level;
  1510. int malertpu_stren;
  1511. int malertsync_bypass;
  1512. int malertdisable_val_defval = 1;
  1513. uint32_t addr;
  1514. if (input->basic.dram_type == DDR4 && input->adv.mem_alert_en == 1) {
  1515. malertpu_en = 1;
  1516. malertrx_en = 1;
  1517. malertpu_stren = input->adv.mem_alert_puimp;
  1518. malertvref_level = input->adv.mem_alert_vref_level;
  1519. malertsync_bypass = input->adv.mem_alert_sync_bypass;
  1520. mem_alert_control = malertdisable_val_defval << 14 |
  1521. malertrx_en << 13 |
  1522. malertpu_en << 12 |
  1523. malertpu_stren << 8 |
  1524. malertvref_level;
  1525. mem_alert_control2 = malertsync_bypass <<
  1526. csr_malertsync_bypass_lsb;
  1527. addr = t_master | csr_mem_alert_control_addr;
  1528. phy_io_write16(phy, addr, mem_alert_control);
  1529. addr = t_master | csr_mem_alert_control2_addr;
  1530. phy_io_write16(phy, addr, mem_alert_control2);
  1531. }
  1532. }
  1533. static void prog_dfi_freq_ratio(uint16_t *phy,
  1534. const struct input *input)
  1535. {
  1536. int dfi_freq_ratio;
  1537. uint32_t addr = t_master | csr_dfi_freq_ratio_addr;
  1538. dfi_freq_ratio = input->basic.dfi_freq_ratio;
  1539. phy_io_write16(phy, addr, dfi_freq_ratio);
  1540. }
  1541. static void prog_tristate_mode_ca(uint16_t *phy,
  1542. const struct input *input)
  1543. {
  1544. int tristate_mode_ca;
  1545. int dis_dyn_adr_tri;
  1546. int ddr2tmode;
  1547. int ck_dis_val_def = 1;
  1548. uint32_t addr = t_master | csr_tristate_mode_ca_addr;
  1549. dis_dyn_adr_tri = input->adv.dis_dyn_adr_tri;
  1550. ddr2tmode = input->adv.is2ttiming;
  1551. tristate_mode_ca = ck_dis_val_def << csr_ck_dis_val_lsb |
  1552. ddr2tmode << csr_ddr2tmode_lsb |
  1553. dis_dyn_adr_tri << csr_dis_dyn_adr_tri_lsb;
  1554. phy_io_write16(phy, addr, tristate_mode_ca);
  1555. }
  1556. static void prog_dfi_xlat(uint16_t *phy,
  1557. const struct input *input)
  1558. {
  1559. uint16_t loop_vector;
  1560. int dfifreqxlat_dat;
  1561. int pllbypass_dat;
  1562. uint32_t addr;
  1563. /* fIXME: Shall unused P1, P2, P3 be bypassed? */
  1564. pllbypass_dat = input->basic.pll_bypass; /* only [0] is used */
  1565. for (loop_vector = 0; loop_vector < 8; loop_vector++) {
  1566. if (loop_vector == 0) {
  1567. dfifreqxlat_dat = pllbypass_dat + 0x5555;
  1568. } else if (loop_vector == 7) {
  1569. dfifreqxlat_dat = 0xf000;
  1570. } else {
  1571. dfifreqxlat_dat = 0x5555;
  1572. }
  1573. addr = t_master | (csr_dfi_freq_xlat0_addr + loop_vector);
  1574. phy_io_write16(phy, addr, dfifreqxlat_dat);
  1575. }
  1576. }
  1577. static void prog_dbyte_misc_mode(uint16_t *phy,
  1578. const struct input *input,
  1579. const struct ddr4u1d *msg)
  1580. {
  1581. int dbyte_misc_mode;
  1582. int dq_dqs_rcv_cntrl1;
  1583. int dq_dqs_rcv_cntrl1_1;
  1584. int byte, c_addr;
  1585. uint32_t addr;
  1586. dbyte_misc_mode = 0x1 << csr_dbyte_disable_lsb;
  1587. dq_dqs_rcv_cntrl1 = 0x1ff << csr_power_down_rcvr_lsb |
  1588. 0x1 << csr_power_down_rcvr_dqs_lsb |
  1589. 0x1 << csr_rx_pad_standby_en_lsb;
  1590. dq_dqs_rcv_cntrl1_1 = (0x100 << csr_power_down_rcvr_lsb |
  1591. csr_rx_pad_standby_en_mask);
  1592. for (byte = 0; byte < input->basic.num_dbyte; byte++) {
  1593. c_addr = byte << 12;
  1594. if (byte <= input->basic.num_active_dbyte_dfi0 - 1) {
  1595. /* disable RDBI lane if not used. */
  1596. if ((input->basic.dram_data_width != 4) &&
  1597. (((msg->mr5 >> 12) & 0x1) == 0)) {
  1598. addr = t_dbyte
  1599. | c_addr
  1600. | csr_dq_dqs_rcv_cntrl1_addr;
  1601. phy_io_write16(phy, addr, dq_dqs_rcv_cntrl1_1);
  1602. }
  1603. } else {
  1604. addr = t_dbyte | c_addr | csr_dbyte_misc_mode_addr;
  1605. phy_io_write16(phy, addr, dbyte_misc_mode);
  1606. addr = t_dbyte | c_addr | csr_dq_dqs_rcv_cntrl1_addr;
  1607. phy_io_write16(phy, addr, dq_dqs_rcv_cntrl1);
  1608. }
  1609. }
  1610. }
  1611. static void prog_master_x4config(uint16_t *phy,
  1612. const struct input *input)
  1613. {
  1614. int master_x4config;
  1615. int x4tg;
  1616. uint32_t addr = t_master | csr_master_x4config_addr;
  1617. x4tg = input->basic.dram_data_width == 4 ? 0xf : 0;
  1618. master_x4config = x4tg << csr_x4tg_lsb;
  1619. phy_io_write16(phy, addr, master_x4config);
  1620. }
  1621. static void prog_dmipin_present(uint16_t *phy,
  1622. const struct input *input,
  1623. const struct ddr4u1d *msg)
  1624. {
  1625. int dmipin_present;
  1626. uint32_t addr = t_master | csr_dmipin_present_addr;
  1627. dmipin_present = (msg->mr5 >> 12) & 0x1;
  1628. phy_io_write16(phy, addr, dmipin_present);
  1629. }
  1630. static void prog_dfi_phyupd(uint16_t *phy,
  1631. const struct input *input)
  1632. {
  1633. int dfiphyupd_dat;
  1634. uint32_t addr;
  1635. addr = t_master | (csr_dfiphyupd_addr);
  1636. dfiphyupd_dat = phy_io_read16(phy, addr) &
  1637. ~csr_dfiphyupd_threshold_mask;
  1638. phy_io_write16(phy, addr, dfiphyupd_dat);
  1639. }
  1640. static void prog_cal_misc2(uint16_t *phy,
  1641. const struct input *input)
  1642. {
  1643. int cal_misc2_dat, cal_drv_pdth_data, cal_offsets_dat;
  1644. uint32_t addr;
  1645. addr = t_master | (csr_cal_misc2_addr);
  1646. cal_misc2_dat = phy_io_read16(phy, addr) |
  1647. (1 << csr_cal_misc2_err_dis);
  1648. phy_io_write16(phy, addr, cal_misc2_dat);
  1649. addr = t_master | (csr_cal_offsets_addr);
  1650. cal_drv_pdth_data = 0x9 << 6;
  1651. cal_offsets_dat = (phy_io_read16(phy, addr) & ~csr_cal_drv_pdth_mask)
  1652. | cal_drv_pdth_data;
  1653. phy_io_write16(phy, addr, cal_offsets_dat);
  1654. }
  1655. static int c_init_phy_config(uint16_t **phy_ptr,
  1656. unsigned int ip_rev,
  1657. const struct input *input,
  1658. const void *msg)
  1659. {
  1660. int i;
  1661. uint16_t *phy;
  1662. __unused const soc_info_t *soc_info;
  1663. for (i = 0; i < NUM_OF_DDRC; i++) {
  1664. phy = phy_ptr[i];
  1665. if (phy == NULL) {
  1666. continue;
  1667. }
  1668. debug("Initialize PHY %d config\n", i);
  1669. prog_dfi_phyupd(phy, input);
  1670. prog_cal_misc2(phy, input);
  1671. prog_tx_pre_drv_mode(phy, input);
  1672. prog_atx_pre_drv_mode(phy, input);
  1673. prog_enable_cs_multicast(phy, input); /* rdimm and lrdimm */
  1674. prog_dfi_rd_data_cs_dest_map(phy, ip_rev, input, msg);
  1675. prog_pll_ctrl2(phy, input);
  1676. #ifdef DDR_PLL_FIX
  1677. soc_info = get_soc_info();
  1678. debug("SOC_SI_REV = %x\n", soc_info->svr_reg.bf.maj_ver);
  1679. if (soc_info->svr_reg.bf.maj_ver == 1) {
  1680. prog_pll_pwr_dn(phy, input);
  1681. /*Enable FFE aka TxEqualizationMode for rev1 SI*/
  1682. phy_io_write16(phy, 0x010048, 0x1);
  1683. }
  1684. #endif
  1685. prog_ard_ptr_init_val(phy, input);
  1686. prog_dqs_preamble_control(phy, input);
  1687. prog_dll_lck_param(phy, input);
  1688. prog_dll_gain_ctl(phy, input);
  1689. prog_proc_odt_time_ctl(phy, input);
  1690. prog_tx_odt_drv_stren(phy, input);
  1691. prog_tx_impedance_ctrl1(phy, input);
  1692. prog_atx_impedance(phy, input);
  1693. prog_dfi_mode(phy, input);
  1694. prog_dfi_camode(phy, input);
  1695. prog_cal_drv_str0(phy, input);
  1696. prog_cal_uclk_info(phy, input);
  1697. prog_cal_rate(phy, input);
  1698. prog_vref_in_global(phy, input, msg);
  1699. prog_dq_dqs_rcv_cntrl(phy, input);
  1700. prog_mem_alert_control(phy, input);
  1701. prog_dfi_freq_ratio(phy, input);
  1702. prog_tristate_mode_ca(phy, input);
  1703. prog_dfi_xlat(phy, input);
  1704. prog_dbyte_misc_mode(phy, input, msg);
  1705. prog_master_x4config(phy, input);
  1706. prog_dmipin_present(phy, input, msg);
  1707. prog_acx4_anib_dis(phy, input);
  1708. }
  1709. return 0;
  1710. }
  1711. static uint32_t get_mail(uint16_t *phy, int stream)
  1712. {
  1713. int timeout;
  1714. uint32_t mail = 0U;
  1715. timeout = TIMEOUTDEFAULT;
  1716. while (((--timeout) != 0) &&
  1717. ((phy_io_read16(phy, t_apbonly | csr_uct_shadow_regs)
  1718. & uct_write_prot_shadow_mask) != 0)) {
  1719. mdelay(10);
  1720. }
  1721. if (timeout == 0) {
  1722. ERROR("Timeout getting mail from PHY\n");
  1723. return 0xFFFF;
  1724. }
  1725. mail = phy_io_read16(phy, t_apbonly |
  1726. csr_uct_write_only_shadow);
  1727. if (stream != 0) {
  1728. mail |= phy_io_read16(phy, t_apbonly |
  1729. csr_uct_dat_write_only_shadow) << 16;
  1730. }
  1731. /* Ack */
  1732. phy_io_write16(phy, t_apbonly | csr_dct_write_prot, 0);
  1733. timeout = TIMEOUTDEFAULT;
  1734. while (((--timeout) != 0) &&
  1735. ((phy_io_read16(phy, t_apbonly | csr_uct_shadow_regs)
  1736. & uct_write_prot_shadow_mask) == 0)) {
  1737. mdelay(1);
  1738. }
  1739. if (timeout == 0) {
  1740. ERROR("Timeout ack PHY mail\n");
  1741. }
  1742. /* completed */
  1743. phy_io_write16(phy, t_apbonly | csr_dct_write_prot, 1U);
  1744. return mail;
  1745. }
  1746. #ifdef DDR_PHY_DEBUG
  1747. static const char *lookup_msg(uint32_t index, int train2d)
  1748. {
  1749. int i;
  1750. int size;
  1751. const struct phy_msg *messages;
  1752. const char *ptr = NULL;
  1753. if (train2d != 0) {
  1754. messages = messages_2d;
  1755. size = ARRAY_SIZE(messages_2d);
  1756. } else {
  1757. messages = messages_1d;
  1758. size = ARRAY_SIZE(messages_1d);
  1759. }
  1760. for (i = 0; i < size; i++) {
  1761. if (messages[i].index == index) {
  1762. ptr = messages[i].msg;
  1763. break;
  1764. }
  1765. }
  1766. return ptr;
  1767. }
  1768. #endif
  1769. #define MAX_ARGS 32
  1770. static void decode_stream_message(uint16_t *phy, int train2d)
  1771. {
  1772. uint32_t index __unused;
  1773. __unused const char *format;
  1774. __unused uint32_t args[MAX_ARGS];
  1775. __unused int i;
  1776. #ifdef DDR_PHY_DEBUG
  1777. index = get_mail(phy, 1);
  1778. if ((index & 0xffff) > MAX_ARGS) { /* up to MAX_ARGS args so far */
  1779. printf("Program error in %s\n", __func__);
  1780. }
  1781. for (i = 0; i < (index & 0xffff) && i < MAX_ARGS; i++) {
  1782. args[i] = get_mail(phy, 1);
  1783. }
  1784. format = lookup_msg(index, train2d);
  1785. if (format != NULL) {
  1786. printf("0x%08x: ", index);
  1787. printf(format, args[0], args[1], args[2], args[3], args[4],
  1788. args[5], args[6], args[7], args[8], args[9], args[10],
  1789. args[11], args[12], args[13], args[14], args[15],
  1790. args[16], args[17], args[18], args[19], args[20],
  1791. args[21], args[22], args[23], args[24], args[25],
  1792. args[26], args[27], args[28], args[29], args[30],
  1793. args[31]);
  1794. }
  1795. #endif
  1796. }
  1797. static int wait_fw_done(uint16_t *phy, int train2d)
  1798. {
  1799. uint32_t mail = 0U;
  1800. while (mail == U(0x0)) {
  1801. mail = get_mail(phy, 0);
  1802. switch (mail) {
  1803. case U(0x7):
  1804. debug("%s Training completed\n", train2d ? "2D" : "1D");
  1805. break;
  1806. case U(0xff):
  1807. debug("%s Training failure\n", train2d ? "2D" : "1D");
  1808. break;
  1809. case U(0x0):
  1810. debug("End of initialization\n");
  1811. mail = 0U;
  1812. break;
  1813. case U(0x1):
  1814. debug("End of fine write leveling\n");
  1815. mail = 0U;
  1816. break;
  1817. case U(0x2):
  1818. debug("End of read enable training\n");
  1819. mail = 0U;
  1820. break;
  1821. case U(0x3):
  1822. debug("End of read delay center optimization\n");
  1823. mail = 0U;
  1824. break;
  1825. case U(0x4):
  1826. debug("End of write delay center optimization\n");
  1827. mail = 0U;
  1828. break;
  1829. case U(0x5):
  1830. debug("End of 2D read delay/voltage center optimztn\n");
  1831. mail = 0U;
  1832. break;
  1833. case U(0x6):
  1834. debug("End of 2D write delay/voltage center optmztn\n");
  1835. mail = 0U;
  1836. break;
  1837. case U(0x8):
  1838. decode_stream_message(phy, train2d);
  1839. mail = 0U;
  1840. break;
  1841. case U(0x9):
  1842. debug("End of max read latency training\n");
  1843. mail = 0U;
  1844. break;
  1845. case U(0xa):
  1846. debug("End of read dq deskew training\n");
  1847. mail = 0U;
  1848. break;
  1849. case U(0xc):
  1850. debug("End of LRDIMM Specific training, including:\n");
  1851. debug("/tDWL, MREP, MRD and MWD\n");
  1852. mail = 0U;
  1853. break;
  1854. case U(0xd):
  1855. debug("End of CA training\n");
  1856. mail = 0U;
  1857. break;
  1858. case U(0xfd):
  1859. debug("End of MPR read delay center optimization\n");
  1860. mail = 0U;
  1861. break;
  1862. case U(0xfe):
  1863. debug("End of Write leveling coarse delay\n");
  1864. mail = 0U;
  1865. break;
  1866. case U(0xffff):
  1867. debug("Timed out\n");
  1868. break;
  1869. default:
  1870. mail = 0U;
  1871. break;
  1872. }
  1873. }
  1874. if (mail == U(0x7)) {
  1875. return 0;
  1876. } else if (mail == U(0xff)) {
  1877. return -EIO;
  1878. } else if (mail == U(0xffff)) {
  1879. return -ETIMEDOUT;
  1880. }
  1881. debug("PHY_GEN2 FW: Unxpected mail = 0x%x\n", mail);
  1882. return -EINVAL;
  1883. }
  1884. static int g_exec_fw(uint16_t **phy_ptr, int train2d, struct input *input)
  1885. {
  1886. int ret = -EINVAL;
  1887. int i;
  1888. uint16_t *phy;
  1889. for (i = 0; i < NUM_OF_DDRC; i++) {
  1890. phy = phy_ptr[i];
  1891. if (phy == NULL) {
  1892. continue;
  1893. }
  1894. debug("Applying PLL optimal settings\n");
  1895. prog_pll_ctrl2(phy, input);
  1896. prog_pll_ctrl(phy, input);
  1897. phy_io_write16(phy,
  1898. t_apbonly | csr_micro_cont_mux_sel_addr,
  1899. 0x1);
  1900. phy_io_write16(phy,
  1901. t_apbonly | csr_micro_reset_addr,
  1902. csr_reset_to_micro_mask |
  1903. csr_stall_to_micro_mask);
  1904. phy_io_write16(phy,
  1905. t_apbonly | csr_micro_reset_addr,
  1906. csr_stall_to_micro_mask);
  1907. phy_io_write16(phy,
  1908. t_apbonly | csr_micro_reset_addr,
  1909. 0);
  1910. ret = wait_fw_done(phy, train2d);
  1911. if (ret == -ETIMEDOUT) {
  1912. ERROR("Wait timed out: Firmware execution on PHY %d\n",
  1913. i);
  1914. }
  1915. }
  1916. return ret;
  1917. }
  1918. static inline int send_fw(uint16_t *phy,
  1919. uint32_t dst,
  1920. uint16_t *img,
  1921. uint32_t size)
  1922. {
  1923. uint32_t i;
  1924. if ((size % 2U) != 0U) {
  1925. ERROR("Wrong image size 0x%x\n", size);
  1926. return -EINVAL;
  1927. }
  1928. for (i = 0U; i < size / 2; i++) {
  1929. phy_io_write16(phy, dst + i, *(img + i));
  1930. }
  1931. return 0;
  1932. }
  1933. static int load_fw(uint16_t **phy_ptr,
  1934. struct input *input,
  1935. int train2d,
  1936. void *msg,
  1937. size_t len,
  1938. uintptr_t phy_gen2_fw_img_buf,
  1939. int (*img_loadr)(unsigned int, uintptr_t *, uint32_t *),
  1940. uint32_t warm_boot_flag)
  1941. {
  1942. uint32_t imem_id, dmem_id;
  1943. uintptr_t image_buf;
  1944. uint32_t size;
  1945. int ret;
  1946. int i;
  1947. uint16_t *phy;
  1948. switch (input->basic.dimm_type) {
  1949. case UDIMM:
  1950. case SODIMM:
  1951. case NODIMM:
  1952. imem_id = train2d ? DDR_IMEM_UDIMM_2D_IMAGE_ID :
  1953. DDR_IMEM_UDIMM_1D_IMAGE_ID;
  1954. dmem_id = train2d ? DDR_DMEM_UDIMM_2D_IMAGE_ID :
  1955. DDR_DMEM_UDIMM_1D_IMAGE_ID;
  1956. break;
  1957. case RDIMM:
  1958. imem_id = train2d ? DDR_IMEM_RDIMM_2D_IMAGE_ID :
  1959. DDR_IMEM_RDIMM_1D_IMAGE_ID;
  1960. dmem_id = train2d ? DDR_DMEM_RDIMM_2D_IMAGE_ID :
  1961. DDR_DMEM_RDIMM_1D_IMAGE_ID;
  1962. break;
  1963. default:
  1964. ERROR("Unsupported DIMM type\n");
  1965. return -EINVAL;
  1966. }
  1967. size = PHY_GEN2_MAX_IMAGE_SIZE;
  1968. image_buf = (uintptr_t)phy_gen2_fw_img_buf;
  1969. ret = img_loadr(imem_id, &image_buf, &size);
  1970. if (ret != 0) {
  1971. ERROR("Failed to load %d firmware.\n", imem_id);
  1972. return ret;
  1973. }
  1974. debug("Loaded Imaged id %d of size %x at address %lx\n",
  1975. imem_id, size, image_buf);
  1976. for (i = 0; i < NUM_OF_DDRC; i++) {
  1977. phy = phy_ptr[i];
  1978. if (phy == NULL) {
  1979. continue;
  1980. }
  1981. if (warm_boot_flag != DDR_WARM_BOOT) {
  1982. if (train2d == 0) {
  1983. phy_io_write16(phy, t_master |
  1984. csr_mem_reset_l_addr,
  1985. csr_protect_mem_reset_mask);
  1986. }
  1987. }
  1988. /* Enable access to the internal CSRs */
  1989. phy_io_write16(phy, t_apbonly | csr_micro_cont_mux_sel_addr, 0);
  1990. ret = send_fw(phy, PHY_GEN2_IMEM_ADDR,
  1991. (uint16_t *)image_buf, size);
  1992. if (ret != 0) {
  1993. return ret;
  1994. }
  1995. }
  1996. size = PHY_GEN2_MAX_IMAGE_SIZE;
  1997. image_buf = (uintptr_t)phy_gen2_fw_img_buf;
  1998. ret = img_loadr(dmem_id, &image_buf, &size);
  1999. if (ret != 0) {
  2000. ERROR("Failed to load %d firmware.\n", dmem_id);
  2001. return ret;
  2002. }
  2003. debug("Loaded Imaged id %d of size %x at address %lx\n",
  2004. dmem_id, size, image_buf);
  2005. image_buf += len;
  2006. size -= len;
  2007. for (i = 0; i < NUM_OF_DDRC; i++) {
  2008. phy = phy_ptr[i];
  2009. if (phy == NULL) {
  2010. continue;
  2011. }
  2012. ret = send_fw(phy, PHY_GEN2_DMEM_ADDR, msg, len);
  2013. if (ret != 0) {
  2014. return ret;
  2015. }
  2016. ret = send_fw(phy, PHY_GEN2_DMEM_ADDR + len / 2,
  2017. (uint16_t *)image_buf, size);
  2018. if (ret != 0) {
  2019. return ret;
  2020. }
  2021. }
  2022. return ret;
  2023. }
  2024. static void parse_odt(const unsigned int val,
  2025. const int read,
  2026. const int i,
  2027. const unsigned int cs_d0,
  2028. const unsigned int cs_d1,
  2029. unsigned int *odt)
  2030. {
  2031. int shift = read ? 4 : 0;
  2032. int j;
  2033. if (i < 0 || i > 3) {
  2034. printf("Error: invalid chip-select value\n");
  2035. return;
  2036. }
  2037. switch (val) {
  2038. case DDR_ODT_CS:
  2039. odt[i] |= (1 << i) << shift;
  2040. break;
  2041. case DDR_ODT_ALL_OTHER_CS:
  2042. for (j = 0; j < DDRC_NUM_CS; j++) {
  2043. if (i == j) {
  2044. continue;
  2045. }
  2046. if (((cs_d0 | cs_d1) & (1 << j)) == 0) {
  2047. continue;
  2048. }
  2049. odt[j] |= (1 << i) << shift;
  2050. }
  2051. break;
  2052. case DDR_ODT_CS_AND_OTHER_DIMM:
  2053. odt[i] |= (1 << i) << 4;
  2054. /* fallthrough */
  2055. case DDR_ODT_OTHER_DIMM:
  2056. for (j = 0; j < DDRC_NUM_CS; j++) {
  2057. if ((((cs_d0 & (1 << i)) != 0) &&
  2058. ((cs_d1 & (1 << j)) != 0)) ||
  2059. (((cs_d1 & (1 << i)) != 0) &&
  2060. ((cs_d0 & (1 << j)) != 0))) {
  2061. odt[j] |= (1 << i) << shift;
  2062. }
  2063. }
  2064. break;
  2065. case DDR_ODT_ALL:
  2066. for (j = 0; j < DDRC_NUM_CS; j++) {
  2067. if (((cs_d0 | cs_d1) & (1 << j)) == 0) {
  2068. continue;
  2069. }
  2070. odt[j] |= (1 << i) << shift;
  2071. }
  2072. break;
  2073. case DDR_ODT_SAME_DIMM:
  2074. for (j = 0; j < DDRC_NUM_CS; j++) {
  2075. if ((((cs_d0 & (1 << i)) != 0) &&
  2076. ((cs_d0 & (1 << j)) != 0)) ||
  2077. (((cs_d1 & (1 << i)) != 0) &&
  2078. ((cs_d1 & (1 << j)) != 0))) {
  2079. odt[j] |= (1 << i) << shift;
  2080. }
  2081. }
  2082. break;
  2083. case DDR_ODT_OTHER_CS_ONSAMEDIMM:
  2084. for (j = 0; j < DDRC_NUM_CS; j++) {
  2085. if (i == j) {
  2086. continue;
  2087. }
  2088. if ((((cs_d0 & (1 << i)) != 0) &&
  2089. ((cs_d0 & (1 << j)) != 0)) ||
  2090. (((cs_d1 & (1 << i)) != 0) &&
  2091. ((cs_d1 & (1 << j)) != 0))) {
  2092. odt[j] |= (1 << i) << shift;
  2093. }
  2094. }
  2095. break;
  2096. case DDR_ODT_NEVER:
  2097. break;
  2098. default:
  2099. break;
  2100. }
  2101. }
  2102. #ifdef DEBUG_DDR_INPUT_CONFIG
  2103. char *dram_types_str[] = {
  2104. "DDR4",
  2105. "DDR3",
  2106. "LDDDR4",
  2107. "LPDDR3",
  2108. "LPDDR2",
  2109. "DDR5"
  2110. };
  2111. char *dimm_types_str[] = {
  2112. "UDIMM",
  2113. "SODIMM",
  2114. "RDIMM",
  2115. "LRDIMM",
  2116. "NODIMM",
  2117. };
  2118. static void print_jason_format(struct input *input,
  2119. struct ddr4u1d *msg_1d,
  2120. struct ddr4u2d *msg_2d)
  2121. {
  2122. printf("\n{");
  2123. printf("\n \"dram_type\": \"%s\",", dram_types_str[input->basic.dram_type]);
  2124. printf("\n \"dimm_type\": \"%s\",", dimm_types_str[input->basic.dimm_type]);
  2125. printf("\n \"hard_macro_ver\": \"%d\",", input->basic.hard_macro_ver);
  2126. printf("\n \"num_dbyte\": \"0x%04x\",", (unsigned int)input->basic.num_dbyte);
  2127. printf("\n \"num_active_dbyte_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_active_dbyte_dfi0);
  2128. printf("\n \"num_anib\": \"0x%04x\",", (unsigned int)input->basic.num_anib);
  2129. printf("\n \"num_rank_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_rank_dfi0);
  2130. printf("\n \"num_pstates\": \"0x%04x\",", (unsigned int)input->basic.num_pstates);
  2131. printf("\n \"frequency\": \"%d\",", input->basic.frequency);
  2132. printf("\n \"pll_bypass\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio);
  2133. printf("\n \"dfi_freq_ratio\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio);
  2134. printf("\n \"dfi1_exists\": \"0x%04x\",", (unsigned int)input->basic.dfi1exists);
  2135. printf("\n \"dram_data_width\": \"0x%04x\",", (unsigned int)input->basic.dram_data_width);
  2136. printf("\n \"dram_byte_swap\": \"0x%04x\",", (unsigned int)input->adv.dram_byte_swap);
  2137. printf("\n \"ext_cal_res_val\": \"0x%04x\",", (unsigned int)input->adv.ext_cal_res_val);
  2138. printf("\n \"tx_slew_rise_dq\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_rise_dq);
  2139. printf("\n \"tx_slew_fall_dq\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_fall_dq);
  2140. printf("\n \"tx_slew_rise_ac\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_rise_ac);
  2141. printf("\n \"tx_slew_fall_ac\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_fall_ac);
  2142. printf("\n \"odt_impedance\": \"%d\",", input->adv.odtimpedance);
  2143. printf("\n \"tx_impedance\": \"%d\",", input->adv.tx_impedance);
  2144. printf("\n \"atx_impedance\": \"%d\",", input->adv.atx_impedance);
  2145. printf("\n \"mem_alert_en\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_en);
  2146. printf("\n \"mem_alert_pu_imp\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_puimp);
  2147. printf("\n \"mem_alert_vref_level\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_vref_level);
  2148. printf("\n \"mem_alert_sync_bypass\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_sync_bypass);
  2149. printf("\n \"cal_interval\": \"0x%04x\",", (unsigned int)input->adv.cal_interval);
  2150. printf("\n \"cal_once\": \"0x%04x\",", (unsigned int)input->adv.cal_once);
  2151. printf("\n \"dis_dyn_adr_tri\": \"0x%04x\",", (unsigned int)input->adv.dis_dyn_adr_tri);
  2152. printf("\n \"is2t_timing\": \"0x%04x\",", (unsigned int)input->adv.is2ttiming);
  2153. printf("\n \"d4rx_preabmle_length\": \"0x%04x\",", (unsigned int)input->adv.d4rx_preamble_length);
  2154. printf("\n \"d4tx_preamble_length\": \"0x%04x\",", (unsigned int)input->adv.d4tx_preamble_length);
  2155. printf("\n \"msg_misc\": \"0x%02x\",", (unsigned int)msg_1d->msg_misc);
  2156. printf("\n \"reserved00\": \"0x%01x\",", (unsigned int)msg_1d->reserved00);
  2157. printf("\n \"hdt_ctrl\": \"0x%02x\",", (unsigned int)msg_1d->hdt_ctrl);
  2158. printf("\n \"cs_present\": \"0x%02x\",", (unsigned int)msg_1d->cs_present);
  2159. printf("\n \"phy_vref\": \"0x%02x\",", (unsigned int)msg_1d->phy_vref);
  2160. printf("\n \"dfi_mrl_margin\": \"0x%02x\",", (unsigned int)msg_1d->dfimrlmargin);
  2161. printf("\n \"addr_mirror\": \"0x%02x\",", (unsigned int)msg_1d->addr_mirror);
  2162. printf("\n \"wr_odt_pat_rank0\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl0 & 0x0f));
  2163. printf("\n \"wr_odt_pat_rank1\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl1 & 0x0f));
  2164. printf("\n \"wr_odt_pat_rank2\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl2 & 0x0f));
  2165. printf("\n \"wr_odt_pat_rank3\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl3 & 0x0f));
  2166. printf("\n \"rd_odt_pat_rank0\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl0 & 0xf0));
  2167. printf("\n \"rd_odt_pat_rank1\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl1 & 0xf0));
  2168. printf("\n \"rd_odt_pat_rank2\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl2 & 0xf0));
  2169. printf("\n \"rd_odt_pat_rank3\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl3 & 0xf0));
  2170. printf("\n \"d4_misc\": \"0x%01x\",", (unsigned int)msg_1d->d4misc);
  2171. printf("\n \"share_2d_vref_results\": \"0x%01x\",", (unsigned int)msg_1d->share2dvref_result);
  2172. printf("\n \"sequence_ctrl\": \"0x%04x\",", (unsigned int)msg_1d->sequence_ctrl);
  2173. printf("\n \"mr0\": \"0x%04x\",", (unsigned int)msg_1d->mr0);
  2174. printf("\n \"mr1\": \"0x%04x\",", (unsigned int)msg_1d->mr1);
  2175. printf("\n \"mr2\": \"0x%04x\",", (unsigned int)msg_1d->mr2);
  2176. printf("\n \"mr3\": \"0x%04x\",", (unsigned int)msg_1d->mr3);
  2177. printf("\n \"mr4\": \"0x%04x\",", (unsigned int)msg_1d->mr4);
  2178. printf("\n \"mr5\": \"0x%04x\",", (unsigned int)msg_1d->mr5);
  2179. printf("\n \"mr6\": \"0x%04x\",", (unsigned int)msg_1d->mr6);
  2180. printf("\n \"alt_cal_l\": \"0x%04x\",", (unsigned int)msg_1d->alt_cas_l);
  2181. printf("\n \"alt_wcal_l\": \"0x%04x\",", (unsigned int)msg_1d->alt_wcas_l);
  2182. printf("\n \"sequence_ctrl_2d\": \"0x%04x\",", (unsigned int)msg_2d->sequence_ctrl);
  2183. printf("\n \"rtt_nom_wr_park0\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park0);
  2184. printf("\n \"rtt_nom_wr_park1\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park1);
  2185. printf("\n \"rtt_nom_wr_park2\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park2);
  2186. printf("\n \"rtt_nom_wr_park3\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park3);
  2187. printf("\n \"rtt_nom_wr_park4\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park4);
  2188. printf("\n \"rtt_nom_wr_park5\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park5);
  2189. printf("\n \"rtt_nom_wr_park6\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park6);
  2190. printf("\n \"rtt_nom_wr_park7\": \"0x%01x\"", (unsigned int)msg_1d->rtt_nom_wr_park7);
  2191. printf("\n}");
  2192. printf("\n");
  2193. }
  2194. #endif
  2195. int compute_ddr_phy(struct ddr_info *priv)
  2196. {
  2197. const unsigned long clk = priv->clk;
  2198. const struct memctl_opt *popts = &priv->opt;
  2199. const struct ddr_conf *conf = &priv->conf;
  2200. const struct dimm_params *dimm_param = &priv->dimm;
  2201. struct ddr_cfg_regs *regs = &priv->ddr_reg;
  2202. int ret;
  2203. static struct input input;
  2204. static struct ddr4u1d msg_1d;
  2205. static struct ddr4u2d msg_2d;
  2206. unsigned int i;
  2207. unsigned int odt_rd, odt_wr;
  2208. __unused const soc_info_t *soc_info;
  2209. #ifdef NXP_APPLY_MAX_CDD
  2210. unsigned int tcfg0, tcfg4, rank;
  2211. #ifdef NXP_WARM_BOOT
  2212. struct ddr_ctrl_reg_values ddrctrl_regs;
  2213. #endif
  2214. #endif
  2215. if (dimm_param == NULL) {
  2216. ERROR("Empty DIMM parameters.\n");
  2217. return -EINVAL;
  2218. }
  2219. zeromem(&input, sizeof(input));
  2220. zeromem(&msg_1d, sizeof(msg_1d));
  2221. zeromem(&msg_2d, sizeof(msg_2d));
  2222. input.basic.dram_type = DDR4;
  2223. /* FIXME: Add condition for LRDIMM */
  2224. input.basic.dimm_type = (dimm_param->rdimm != 0) ? RDIMM : UDIMM;
  2225. input.basic.num_dbyte = dimm_param->primary_sdram_width / 8 +
  2226. dimm_param->ec_sdram_width / 8;
  2227. input.basic.num_active_dbyte_dfi0 = input.basic.num_dbyte;
  2228. input.basic.num_rank_dfi0 = dimm_param->n_ranks;
  2229. input.basic.dram_data_width = dimm_param->device_width;
  2230. input.basic.hard_macro_ver = 0xa;
  2231. input.basic.num_pstates = 1;
  2232. input.basic.dfi_freq_ratio = 1;
  2233. input.basic.num_anib = 0xc;
  2234. input.basic.train2d = popts->skip2d ? 0 : 1;
  2235. input.basic.frequency = (int) (clk / 2000000ul);
  2236. debug("frequency = %dMHz\n", input.basic.frequency);
  2237. input.cs_d0 = conf->cs_on_dimm[0];
  2238. #if DDRC_NUM_DIMM > 1
  2239. input.cs_d1 = conf->cs_on_dimm[1];
  2240. #endif
  2241. input.mirror = dimm_param->mirrored_dimm;
  2242. input.mr[0] = regs->sdram_mode[0] & U(0xffff);
  2243. input.mr[1] = regs->sdram_mode[0] >> 16U;
  2244. input.mr[2] = regs->sdram_mode[1] >> 16U;
  2245. input.mr[3] = regs->sdram_mode[1] & U(0xffff);
  2246. input.mr[4] = regs->sdram_mode[8] >> 16U;
  2247. input.mr[5] = regs->sdram_mode[8] & U(0xffff);
  2248. input.mr[6] = regs->sdram_mode[9] >> 16U;
  2249. input.vref = popts->vref_phy;
  2250. debug("Vref_phy = %d percent\n", (input.vref * 100U) >> 7U);
  2251. for (i = 0U; i < DDRC_NUM_CS; i++) {
  2252. if ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) == 0U) {
  2253. continue;
  2254. }
  2255. odt_rd = (regs->cs[i].config >> 20U) & U(0x7);
  2256. odt_wr = (regs->cs[i].config >> 16U) & U(0x7);
  2257. parse_odt(odt_rd, true, i, input.cs_d0, input.cs_d1,
  2258. input.odt);
  2259. parse_odt(odt_wr, false, i, input.cs_d0, input.cs_d1,
  2260. input.odt);
  2261. }
  2262. /* Do not set sdram_cfg[RD_EN] or sdram_cfg2[RCW_EN] for RDIMM */
  2263. if (dimm_param->rdimm != 0U) {
  2264. regs->sdram_cfg[0] &= ~(1 << 28U);
  2265. regs->sdram_cfg[1] &= ~(1 << 2U);
  2266. input.rcw[0] = (regs->sdram_rcw[0] >> 28U) & U(0xf);
  2267. input.rcw[1] = (regs->sdram_rcw[0] >> 24U) & U(0xf);
  2268. input.rcw[2] = (regs->sdram_rcw[0] >> 20U) & U(0xf);
  2269. input.rcw[3] = (regs->sdram_rcw[0] >> 16U) & U(0xf);
  2270. input.rcw[4] = (regs->sdram_rcw[0] >> 12U) & U(0xf);
  2271. input.rcw[5] = (regs->sdram_rcw[0] >> 8U) & U(0xf);
  2272. input.rcw[6] = (regs->sdram_rcw[0] >> 4U) & U(0xf);
  2273. input.rcw[7] = (regs->sdram_rcw[0] >> 0U) & U(0xf);
  2274. input.rcw[8] = (regs->sdram_rcw[1] >> 28U) & U(0xf);
  2275. input.rcw[9] = (regs->sdram_rcw[1] >> 24U) & U(0xf);
  2276. input.rcw[10] = (regs->sdram_rcw[1] >> 20U) & U(0xf);
  2277. input.rcw[11] = (regs->sdram_rcw[1] >> 16U) & U(0xf);
  2278. input.rcw[12] = (regs->sdram_rcw[1] >> 12U) & U(0xf);
  2279. input.rcw[13] = (regs->sdram_rcw[1] >> 8U) & U(0xf);
  2280. input.rcw[14] = (regs->sdram_rcw[1] >> 4U) & U(0xf);
  2281. input.rcw[15] = (regs->sdram_rcw[1] >> 0U) & U(0xf);
  2282. input.rcw3x = (regs->sdram_rcw[2] >> 8U) & U(0xff);
  2283. }
  2284. input.adv.odtimpedance = popts->odt ? popts->odt : 60;
  2285. input.adv.tx_impedance = popts->phy_tx_impedance ?
  2286. popts->phy_tx_impedance : 28;
  2287. input.adv.atx_impedance = popts->phy_atx_impedance ?
  2288. popts->phy_atx_impedance : 30;
  2289. debug("Initializing input adv data structure\n");
  2290. phy_gen2_init_input(&input);
  2291. debug("Initializing message block\n");
  2292. ret = phy_gen2_msg_init(&msg_1d, &msg_2d, &input);
  2293. if (ret != 0) {
  2294. ERROR("Init msg failed (error code %d)\n", ret);
  2295. return ret;
  2296. }
  2297. ret = c_init_phy_config(priv->phy, priv->ip_rev, &input, &msg_1d);
  2298. if (ret != 0) {
  2299. ERROR("Init PHY failed (error code %d)\n", ret);
  2300. return ret;
  2301. }
  2302. #ifdef NXP_WARM_BOOT
  2303. debug("Warm boot flag value %0x\n", priv->warm_boot_flag);
  2304. if (priv->warm_boot_flag == DDR_WARM_BOOT) {
  2305. debug("Restoring the Phy training data\n");
  2306. // Restore the training data
  2307. ret = restore_phy_training_values(priv->phy,
  2308. PHY_TRAINING_REGS_ON_FLASH,
  2309. priv->num_ctlrs,
  2310. input.basic.train2d
  2311. #ifdef NXP_APPLY_MAX_CDD
  2312. , &ddrctrl_regs
  2313. #endif
  2314. );
  2315. if (ret != 0) {
  2316. ERROR("Restoring of training data failed %d\n", ret);
  2317. return ret;
  2318. }
  2319. #ifdef NXP_APPLY_MAX_CDD
  2320. regs->timing_cfg[0] = ddrctrl_regs.timing_cfg0;
  2321. regs->timing_cfg[4] = ddrctrl_regs.timing_cfg4;
  2322. #endif
  2323. } else {
  2324. #endif
  2325. /* Mapping IMG buffer firstly */
  2326. ret = mmap_add_dynamic_region(priv->phy_gen2_fw_img_buf,
  2327. priv->phy_gen2_fw_img_buf,
  2328. PHY_GEN2_MAX_IMAGE_SIZE,
  2329. MT_MEMORY | MT_RW | MT_SECURE);
  2330. if (ret != 0) {
  2331. ERROR("Failed to add dynamic memory region.\n");
  2332. return ret;
  2333. }
  2334. debug("Load 1D firmware\n");
  2335. ret = load_fw(priv->phy, &input, 0, &msg_1d,
  2336. sizeof(struct ddr4u1d), priv->phy_gen2_fw_img_buf,
  2337. priv->img_loadr, priv->warm_boot_flag);
  2338. if (ret != 0) {
  2339. ERROR("Loading firmware failed (error code %d)\n", ret);
  2340. return ret;
  2341. }
  2342. debug("Execute firmware\n");
  2343. ret = g_exec_fw(priv->phy, 0, &input);
  2344. if (ret != 0) {
  2345. ERROR("Execution FW failed (error code %d)\n", ret);
  2346. }
  2347. #ifdef NXP_APPLY_MAX_CDD
  2348. soc_info = get_soc_info();
  2349. if (soc_info->svr_reg.bf.maj_ver == 2) {
  2350. tcfg0 = regs->timing_cfg[0];
  2351. tcfg4 = regs->timing_cfg[4];
  2352. rank = findrank(conf->cs_in_use);
  2353. get_cdd_val(priv->phy, rank, input.basic.frequency,
  2354. &tcfg0, &tcfg4);
  2355. regs->timing_cfg[0] = tcfg0;
  2356. regs->timing_cfg[4] = tcfg4;
  2357. }
  2358. #endif
  2359. if ((ret == 0) && (input.basic.train2d != 0)) {
  2360. /* 2D training starts here */
  2361. debug("Load 2D firmware\n");
  2362. ret = load_fw(priv->phy, &input, 1, &msg_2d,
  2363. sizeof(struct ddr4u2d),
  2364. priv->phy_gen2_fw_img_buf,
  2365. priv->img_loadr,
  2366. priv->warm_boot_flag);
  2367. if (ret != 0) {
  2368. ERROR("Loading fw failed (err code %d)\n", ret);
  2369. } else {
  2370. debug("Execute 2D firmware\n");
  2371. ret = g_exec_fw(priv->phy, 1, &input);
  2372. if (ret != 0) {
  2373. ERROR("Execution FW failed (err %d)\n",
  2374. ret);
  2375. }
  2376. }
  2377. }
  2378. #ifdef NXP_WARM_BOOT
  2379. if (priv->warm_boot_flag != DDR_WRM_BOOT_NT_SUPPORTED &&
  2380. ret == 0) {
  2381. #ifdef NXP_APPLY_MAX_CDD
  2382. ddrctrl_regs.timing_cfg0 = regs->timing_cfg[0];
  2383. ddrctrl_regs.timing_cfg4 = regs->timing_cfg[4];
  2384. #endif
  2385. debug("save the phy training data\n");
  2386. //Save training data TBD
  2387. ret = save_phy_training_values(priv->phy,
  2388. PHY_TRAINING_REGS_ON_FLASH,
  2389. priv->num_ctlrs,
  2390. input.basic.train2d
  2391. #ifdef NXP_APPLY_MAX_CDD
  2392. , &ddrctrl_regs
  2393. #endif
  2394. );
  2395. if (ret != 0) {
  2396. ERROR("Saving training data failed.");
  2397. ERROR("Warm boot will fail. Error=%d.\n", ret);
  2398. }
  2399. }
  2400. } /* else */
  2401. #endif
  2402. if (ret == 0) {
  2403. debug("Load PIE\n");
  2404. i_load_pie(priv->phy, &input, &msg_1d);
  2405. NOTICE("DDR4 %s with %d-rank %d-bit bus (x%d)\n",
  2406. input.basic.dimm_type == RDIMM ? "RDIMM" :
  2407. input.basic.dimm_type == LRDIMM ? "LRDIMM" :
  2408. "UDIMM",
  2409. dimm_param->n_ranks,
  2410. dimm_param->primary_sdram_width,
  2411. dimm_param->device_width);
  2412. }
  2413. #ifdef DEBUG_DDR_INPUT_CONFIG
  2414. print_jason_format(&input, &msg_1d, &msg_2d);
  2415. #endif
  2416. return ret;
  2417. }