tc-fvp.dtsi 2.0 KB

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  1. /*
  2. * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #define GIC_CTRL_ADDR 2c010000
  7. #define GIC_GICR_OFFSET 0x200000
  8. #define UART_OFFSET 0x1000
  9. #ifdef TC_RESOLUTION_1920X1080P60
  10. #define VENCODER_TIMING_CLK 148500000
  11. #define VENCODER_TIMING \
  12. clock-frequency = <VENCODER_TIMING_CLK>; \
  13. hactive = <1920>; \
  14. vactive = <1080>; \
  15. hfront-porch = <88>; \
  16. hback-porch = <148>; \
  17. hsync-len = <44>; \
  18. vfront-porch = <4>; \
  19. vback-porch = <36>; \
  20. vsync-len = <5>
  21. #else /* TC_RESOLUTION_640X480P60 */
  22. #define VENCODER_TIMING_CLK 25175000
  23. #define VENCODER_TIMING \
  24. clock-frequency = <VENCODER_TIMING_CLK>; \
  25. hactive = <640>; \
  26. vactive = <480>; \
  27. hfront-porch = <16>; \
  28. hback-porch = <48>; \
  29. hsync-len = <96>; \
  30. vfront-porch = <10>; \
  31. vback-porch = <33>; \
  32. vsync-len = <2>
  33. #endif
  34. / {
  35. chosen {
  36. stdout-path = "serial0:115200n8";
  37. };
  38. ethernet: ethernet@ETHERNET_ADDR {
  39. compatible = "smsc,lan91c111";
  40. };
  41. mmci: mmci@MMC_ADDR {
  42. cd-gpios = <&sysreg 0 0>;
  43. };
  44. rtc@RTC_ADDR {
  45. compatible = "arm,pl031", "arm,primecell";
  46. reg = <0x0 ADDRESSIFY(RTC_ADDR) 0x0 0x1000>;
  47. interrupts = <GIC_SPI RTC_INT IRQ_TYPE_LEVEL_HIGH 0>;
  48. clocks = <&soc_refclk>;
  49. clock-names = "apb_pclk";
  50. };
  51. kmi@KMI_0_ADDR {
  52. compatible = "arm,pl050", "arm,primecell";
  53. reg = <0x0 ADDRESSIFY(KMI_0_ADDR) 0x0 0x1000>;
  54. interrupts = <GIC_SPI KMI_0_INT IRQ_TYPE_LEVEL_HIGH 0>;
  55. clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
  56. clock-names = "KMIREFCLK", "apb_pclk";
  57. };
  58. kmi@1c070000 {
  59. compatible = "arm,pl050", "arm,primecell";
  60. reg = <0x0 0x001c070000 0x0 0x1000>;
  61. interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
  62. clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
  63. clock-names = "KMIREFCLK", "apb_pclk";
  64. };
  65. virtio_block@VIRTIO_BLOCK_ADDR {
  66. compatible = "virtio,mmio";
  67. reg = <0x0 ADDRESSIFY(VIRTIO_BLOCK_ADDR) 0x0 0x200>;
  68. /* spec lists this wrong */
  69. interrupts = <GIC_SPI VIRTIO_BLOCK_INT IRQ_TYPE_LEVEL_HIGH 0>;
  70. };
  71. };