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arm-trusted-fir...
/
plat
/
allwinner
/
sun50i_h6
/
include
/
sunxi_mmap.h

sunxi_mmap.h 2.1 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef SUNXI_MMAP_H
    8. 

  8. #define SUNXI_MMAP_H
    9. 

  9. 

  10. /* Memory regions */
    11. 

  11. #define SUNXI_ROM_BASE			0x00000000
    12. 

  12. #define SUNXI_ROM_SIZE			0x00010000
    13. 

  13. #define SUNXI_SRAM_BASE			0x00020000
    14. 

  14. #define SUNXI_SRAM_SIZE			0x000f8000
    15. 

  15. #define SUNXI_SRAM_A1_BASE		0x00020000
    16. 

  16. #define SUNXI_SRAM_A1_SIZE		0x00008000
    17. 

  17. #define SUNXI_SRAM_A2_BASE		0x00100000
    18. 

  18. #define SUNXI_SRAM_A2_BL31_OFFSET	0x00004000
    19. 

  19. #define SUNXI_SRAM_A2_SIZE		0x00018000
    20. 

  20. #define SUNXI_SRAM_C_BASE		0x00028000
    21. 

  21. #define SUNXI_SRAM_C_SIZE		0x0001e000
    22. 

  22. #define SUNXI_DEV_BASE			0x01000000
    23. 

  23. #define SUNXI_DEV_SIZE			0x09000000
    24. 

  24. #define SUNXI_DRAM_BASE			0x40000000
    25. 

  25. #define SUNXI_DRAM_VIRT_BASE		0x0a000000
    26. 

  26. 

  27. /* Memory-mapped devices */
    28. 

  28. #define SUNXI_SYSCON_BASE		0x03000000
    29. 

  29. #define SUNXI_CPUCFG_BASE		0x09010000
    30. 

  30. #define SUNXI_SID_BASE			0x03006000
    31. 

  31. #define SUNXI_DMA_BASE			0x03002000
    32. 

  32. #define SUNXI_MSGBOX_BASE		0x03003000
    33. 

  33. #define SUNXI_CCU_BASE			0x03001000
    34. 

  34. #define SUNXI_PIO_BASE			0x0300b000
    35. 

  35. #define SUNXI_SPC_BASE			0x03008000
    36. 

  36. #define SUNXI_TIMER_BASE		0x03009000
    37. 

  37. #define SUNXI_WDOG_BASE			0x030090a0
    38. 

  38. #define SUNXI_THS_BASE			0x05070400
    39. 

  39. #define SUNXI_UART0_BASE		0x05000000
    40. 

  40. #define SUNXI_UART1_BASE		0x05000400
    41. 

  41. #define SUNXI_UART2_BASE		0x05000800
    42. 

  42. #define SUNXI_UART3_BASE		0x05000c00
    43. 

  43. #define SUNXI_I2C0_BASE			0x05002000
    44. 

  44. #define SUNXI_I2C1_BASE			0x05002400
    45. 

  45. #define SUNXI_I2C2_BASE			0x05002800
    46. 

  46. #define SUNXI_I2C3_BASE			0x05002c00
    47. 

  47. #define SUNXI_SPI0_BASE			0x05010000
    48. 

  48. #define SUNXI_SPI1_BASE			0x05011000
    49. 

  49. #define SUNXI_SCU_BASE			0x03020000
    50. 

  50. #define SUNXI_GICD_BASE			0x03021000
    51. 

  51. #define SUNXI_GICC_BASE			0x03022000
    52. 

  52. #define SUNXI_R_TIMER_BASE		0x07020000
    53. 

  53. #define SUNXI_R_INTC_BASE		0x07021000
    54. 

  54. #define SUNXI_R_WDOG_BASE		0x07020400
    55. 

  55. #define SUNXI_R_PRCM_BASE		0x07010000
    56. 

  56. #define SUNXI_R_TWD_BASE		0x07020800
    57. 

  57. #define SUNXI_R_CPUCFG_BASE		0x07000400
    58. 

  58. #define SUNXI_R_I2C_BASE		0x07081400
    59. 

  59. #define SUNXI_R_RSB_BASE		0x07083000
    60. 

  60. #define SUNXI_R_UART_BASE		0x07080000
    61. 

  61. #define SUNXI_R_PIO_BASE		0x07022000
    62. 

  62. #define SUNXI_CPUSUBSYS_BASE		0x08100000
    63. 

  63. 

  64. #endif /* SUNXI_MMAP_H */
    65.