gxl_common.c 3.2 KB

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  1. /*
  2. * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #include <assert.h>
  7. #include <bl31/interrupt_mgmt.h>
  8. #include <common/bl_common.h>
  9. #include <common/ep_info.h>
  10. #include <lib/mmio.h>
  11. #include <lib/xlat_tables/xlat_tables_v2.h>
  12. #include <platform_def.h>
  13. #include <stdint.h>
  14. /*******************************************************************************
  15. * Platform memory map regions
  16. ******************************************************************************/
  17. #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
  18. AML_NSDRAM0_SIZE, \
  19. MT_MEMORY | MT_RW | MT_NS)
  20. #define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
  21. AML_NSDRAM1_SIZE, \
  22. MT_MEMORY | MT_RW | MT_NS)
  23. #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
  24. AML_SEC_DEVICE0_SIZE, \
  25. MT_DEVICE | MT_RW | MT_SECURE)
  26. #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
  27. AML_SEC_DEVICE1_SIZE, \
  28. MT_DEVICE | MT_RW | MT_SECURE)
  29. #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
  30. AML_TZRAM_SIZE, \
  31. MT_DEVICE | MT_RW | MT_SECURE)
  32. #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
  33. AML_SEC_DEVICE2_SIZE, \
  34. MT_DEVICE | MT_RW | MT_SECURE)
  35. #define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
  36. AML_SEC_DEVICE3_SIZE, \
  37. MT_DEVICE | MT_RW | MT_SECURE)
  38. static const mmap_region_t gxl_mmap[] = {
  39. MAP_NSDRAM0,
  40. MAP_NSDRAM1,
  41. MAP_SEC_DEVICE0,
  42. MAP_SEC_DEVICE1,
  43. MAP_TZRAM,
  44. MAP_SEC_DEVICE2,
  45. MAP_SEC_DEVICE3,
  46. {0}
  47. };
  48. /*******************************************************************************
  49. * Per-image regions
  50. ******************************************************************************/
  51. #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
  52. BL31_END - BL31_BASE, \
  53. MT_MEMORY | MT_RW | MT_SECURE)
  54. #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
  55. BL_CODE_END - BL_CODE_BASE, \
  56. MT_CODE | MT_SECURE)
  57. #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
  58. BL_RO_DATA_END - BL_RO_DATA_BASE, \
  59. MT_RO_DATA | MT_SECURE)
  60. #define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \
  61. BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
  62. MT_DEVICE | MT_RW | MT_SECURE)
  63. /*******************************************************************************
  64. * Function that sets up the translation tables.
  65. ******************************************************************************/
  66. void aml_setup_page_tables(void)
  67. {
  68. #if IMAGE_BL31
  69. const mmap_region_t gxl_bl_mmap[] = {
  70. MAP_BL31,
  71. MAP_BL_CODE,
  72. MAP_BL_RO_DATA,
  73. #if USE_COHERENT_MEM
  74. MAP_BL_COHERENT,
  75. #endif
  76. {0}
  77. };
  78. #endif
  79. mmap_add(gxl_bl_mmap);
  80. mmap_add(gxl_mmap);
  81. init_xlat_tables();
  82. }
  83. /*******************************************************************************
  84. * Function that returns the system counter frequency
  85. ******************************************************************************/
  86. unsigned int plat_get_syscnt_freq2(void)
  87. {
  88. uint32_t val;
  89. val = mmio_read_32(AML_SYS_CPU_CFG7);
  90. val &= 0xFDFFFFFF;
  91. mmio_write_32(AML_SYS_CPU_CFG7, val);
  92. val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
  93. val &= 0xFFFFFE00;
  94. mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
  95. return AML_OSC24M_CLK_IN_HZ;
  96. }