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drivers
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apusys
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mt8188
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apusys_devapc_def.h

apusys_devapc_def.h 5.5 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2023, MediaTek Inc. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef APUSYS_DEVAPC_DEF_H
    8. 

  8. #define APUSYS_DEVAPC_DEF_H
    9. 

  9. 

  10. #include <lib/mmio.h>
    11. 

  11. #include "../devapc/apusys_dapc_v1.h"
    12. 

  12. 

  13. /* NoC */
    14. 

  14. #define SLAVE_MD32_SRAM			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    15. 

  15. 

  16. /* Control */
    17. 

  17. #define SLAVE_VCORE			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    18. 

  18. #define SLAVE_RPC			SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
    19. 

  19. #define SLAVE_PCU			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    20. 

  20. #define SLAVE_AO_CTRL			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    21. 

  21. #define SLAVE_PLL			SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
    22. 

  22. #define SLAVE_ACC			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    23. 

  23. #define SLAVE_SEC			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    24. 

  24. #define SLAVE_ARE0			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    25. 

  25. #define SLAVE_ARE1			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    26. 

  26. #define SLAVE_ARE2			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    27. 

  27. #define SLAVE_UNKNOWN			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    28. 

  28. #define SLAVE_APU_BULK			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    29. 

  29. #define SLAVE_AO_BCRM			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    30. 

  30. #define SLAVE_AO_DAPC_WRAP		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    31. 

  31. #define SLAVE_AO_DAPC_CON		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    32. 

  32. #define SLAVE_RCX_ACX_BULK		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    33. 

  33. #define SLAVE_ACX0_BCRM			SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    34. 

  34. #define SLAVE_RPCTOP_LITE_ACX0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    35. 

  35. #define SLAVE_ACX1_BCRM			SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    36. 

  36. #define SLAVE_RPCTOP_LITE_ACX1		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    37. 

  37. #define SLAVE_RCX_TO_ACX0_0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    38. 

  38. #define SLAVE_RCX_TO_ACX0_1		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    39. 

  39. #define SLAVE_SAE_TO_ACX0_0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    40. 

  40. #define SLAVE_SAE_TO_ACX0_1		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    41. 

  41. #define SLAVE_RCX_TO_ACX1_0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    42. 

  42. #define SLAVE_RCX_TO_ACX1_1		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    43. 

  43. #define SLAVE_SAE_TO_ACX1_0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    44. 

  44. #define SLAVE_SAE_TO_ACX1_1		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    45. 

  45. #define SLAVE_MD32_SYSCTRL0		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    46. 

  46. #define SLAVE_MD32_SYSCTRL1		SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
    47. 

  47. #define SLAVE_MD32_WDT			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    48. 

  48. #define SLAVE_MD32_CACHE		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    49. 

  49. #define SLAVE_NOC_AXI			SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    50. 

  50. #define SLAVE_MD32_DBG			SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    51. 

  51. #define SLAVE_DBG_CRTL			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    52. 

  52. #define SLAVE_IOMMU0_BANK0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    53. 

  53. #define SLAVE_IOMMU0_BANK1		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    54. 

  54. #define SLAVE_IOMMU0_BANK2		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    55. 

  55. #define SLAVE_IOMMU0_BANK3		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    56. 

  56. #define SLAVE_IOMMU0_BANK4		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    57. 

  57. #define SLAVE_IOMMU1_BANK0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
    58. 

  58. #define SLAVE_IOMMU1_BANK1		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    59. 

  59. #define SLAVE_IOMMU1_BANK2		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    60. 

  60. #define SLAVE_IOMMU1_BANK3		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    61. 

  61. #define SLAVE_IOMMU1_BANK4		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    62. 

  62. #define SLAVE_S0_SSC			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    63. 

  63. #define SLAVE_N0_SSC			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    64. 

  64. #define SLAVE_ACP_SSC			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    65. 

  65. #define SLAVE_S1_SSC			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    66. 

  66. #define SLAVE_N1_SSC			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    67. 

  67. #define SLAVE_CFG			SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
    68. 

  68. #define SLAVE_SEMA_STIMER		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    69. 

  69. #define SLAVE_EMI_CFG			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    70. 

  70. #define SLAVE_LOG			SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
    71. 

  71. #define SLAVE_CPE_SENSOR		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    72. 

  72. #define SLAVE_CPE_COEF			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    73. 

  73. #define SLAVE_CPE_CTRL			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    74. 

  74. #define SLAVE_DFD_REG_SOC		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    75. 

  75. #define SLAVE_SENSOR_WRAP_ACX0_DLA0	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    76. 

  76. #define SLAVE_SENSOR_WRAP_ACX0_DLA1	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    77. 

  77. #define SLAVE_SENSOR_WRAP_ACX0_VPU0	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    78. 

  78. #define SLAVE_SENSOR_WRAP_ACX1_DLA0	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    79. 

  79. #define SLAVE_SENSOR_WRAP_ACX1_DLA1	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    80. 

  80. #define SLAVE_SENSOR_WRAP_ACX1_VPU0	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    81. 

  81. #define SLAVE_REVISER			SLAVE_FORBID_EXCEPT_D0_SEC_RW
    82. 

  82. #define SLAVE_NOC			SLAVE_FORBID_EXCEPT_D0_SEC_RW
    83. 

  83. #define SLAVE_BCRM			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    84. 

  84. #define SLAVE_DAPC_WRAP			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    85. 

  85. #define SLAVE_DAPC_CON			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    86. 

  86. #define SLAVE_NOC_DAPC_WRAP		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    87. 

  87. #define SLAVE_NOC_DAPC_CON		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    88. 

  88. #define SLAVE_NOC_BCRM			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    89. 

  89. #define SLAVE_ACS			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
    90. 

  90. #define SLAVE_HSE			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
    91. 

  91. 

  92. 

  93. /* Power Domain: AO */
    94. 

  94. #define APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM	(16)
    95. 

  95. #define APU_CTRL_DAPC_AO_DOM_NUM		(16)
    96. 

  96. #define APU_CTRL_DAPC_AO_SLAVE_NUM		(30)
    97. 

  97. #define DEVAPC_MASK				(0x3U)
    98. 

  98. #define DEVAPC_DOM_SHIFT			(2)
    99. 

  99. 

  100. /* Power Domain: RCX */
    101. 

  101. #define APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM	(16)
    102. 

  102. #define APU_CTRL_DAPC_RCX_DOM_NUM		(16)
    103. 

  103. #define APU_CTRL_DAPC_RCX_SLAVE_NUM		(63)
    104. 

  104. 

  105. #define APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM	(16)
    106. 

  106. #define APU_NOC_DAPC_RCX_DOM_NUM		(16)
    107. 

  107. #define APU_NOC_DAPC_RCX_SLAVE_NUM		(5)
    108. 

  108. 

  109. #endif /* APUSYS_DEVAPC_DEF_H */
    110.