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mt8192
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drivers
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spm
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sleep_def.h

sleep_def.h 7.0 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2020, MediaTek Inc. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef SLEEP_DEF_H
    8. 

  8. #define SLEEP_DEF_H
    9. 

  9. 

  10. /*
    11. 

  11.  * Auto generated by DE, please DO NOT modify this file directly.
    12. 

  12.  */
    13. 

  13. 

  14. /* --- SPM Flag Define --- */
    15. 

  15. #define SPM_FLAG_DISABLE_CPU_PDN			(1U << 0)
    16. 

  16. #define SPM_FLAG_DISABLE_INFRA_PDN			(1U << 1)
    17. 

  17. #define SPM_FLAG_DISABLE_DDRPHY_PDN			(1U << 2)
    18. 

  18. #define SPM_FLAG_DISABLE_VCORE_DVS			(1U << 3)
    19. 

  19. #define SPM_FLAG_DISABLE_VCORE_DFS			(1U << 4)
    20. 

  20. #define SPM_FLAG_DISABLE_COMMON_SCENARIO		(1U << 5)
    21. 

  21. #define SPM_FLAG_DISABLE_BUS_CLK_OFF			(1U << 6)
    22. 

  22. #define SPM_FLAG_DISABLE_ARMPLL_OFF			(1U << 7)
    23. 

  23. #define SPM_FLAG_KEEP_CSYSPWRACK_HIGH			(1U << 8)
    24. 

  24. #define SPM_FLAG_ENABLE_LVTS_WORKAROUND			(1U << 9)
    25. 

  25. #define SPM_FLAG_RUN_COMMON_SCENARIO			(1U << 10)
    26. 

  26. #define SPM_FLAG_RESERVED_BIT11				(1U << 11)
    27. 

  27. #define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP		(1U << 12)
    28. 

  28. #define SPM_FLAG_USE_SRCCLKENO2				(1U << 13)
    29. 

  29. #define SPM_FLAG_ENABLE_6315_CTRL			(1U << 14)
    30. 

  30. #define SPM_FLAG_ENABLE_TIA_WORKAROUND			(1U << 15)
    31. 

  31. #define SPM_FLAG_DISABLE_SYSRAM_SLEEP			(1U << 16)
    32. 

  32. #define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP		(1U << 17)
    33. 

  33. #define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP		(1U << 18)
    34. 

  34. #define SPM_FLAG_ENABLE_MD_MUMTAS			(1U << 19)
    35. 

  35. #define SPM_FLAG_ENABLE_VOLTAGE_BIN			(1U << 20)
    36. 

  36. #define SPM_FLAG_RESERVED_BIT21				(1U << 21)
    37. 

  37. #define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP		(1U << 22)
    38. 

  38. #define SPM_FLAG_DISABLE_SRAM_EVENT			(1U << 23)
    39. 

  39. #define SPM_FLAG_RESERVED_BIT24				(1U << 24)
    40. 

  40. #define SPM_FLAG_RESERVED_BIT25				(1U << 25)
    41. 

  41. #define SPM_FLAG_RESERVED_BIT26				(1U << 26)
    42. 

  42. #define SPM_FLAG_VTCXO_STATE				(1U << 27)
    43. 

  43. #define SPM_FLAG_INFRA_STATE				(1U << 28)
    44. 

  44. #define SPM_FLAG_APSRC_STATE				(1U << 29)
    45. 

  45. #define SPM_FLAG_VRF18_STATE				(1U << 30)
    46. 

  46. #define SPM_FLAG_DDREN_STATE				(1U << 31)
    47. 

  47. /* --- SPM Flag1 Define --- */
    48. 

  48. #define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M		(1U << 0)
    49. 

  49. #define SPM_FLAG1_DISABLE_SYSPLL_OFF			(1U << 1)
    50. 

  50. #define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH		(1U << 2)
    51. 

  51. #define SPM_FLAG1_DISABLE_ULPOSC_OFF			(1U << 3)
    52. 

  52. #define SPM_FLAG1_FW_SET_ULPOSC_ON			(1U << 4)
    53. 

  53. #define SPM_FLAG1_RESERVED_BIT5				(1U << 5)
    54. 

  54. #define SPM_FLAG1_ENABLE_REKICK				(1U << 6)
    55. 

  55. #define SPM_FLAG1_DISABLE_MD26M_CK_OFF			(1U << 7)
    56. 

  56. #define SPM_FLAG1_RESERVED_BIT8				(1U << 8)
    57. 

  57. #define SPM_FLAG1_RESERVED_BIT9				(1U << 9)
    58. 

  58. #define SPM_FLAG1_DISABLE_SRCLKEN_LOW			(1U << 10)
    59. 

  59. #define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH		(1U << 11)
    60. 

  60. #define SPM_FLAG1_RESERVED_BIT12			(1U << 12)
    61. 

  61. #define SPM_FLAG1_RESERVED_BIT13			(1U << 13)
    62. 

  62. #define SPM_FLAG1_RESERVED_BIT14			(1U << 14)
    63. 

  63. #define SPM_FLAG1_RESERVED_BIT15			(1U << 15)
    64. 

  64. #define SPM_FLAG1_RESERVED_BIT16			(1U << 16)
    65. 

  65. #define SPM_FLAG1_RESERVED_BIT17			(1U << 17)
    66. 

  66. #define SPM_FLAG1_RESERVED_BIT18			(1U << 18)
    67. 

  67. #define SPM_FLAG1_RESERVED_BIT19			(1U << 19)
    68. 

  68. #define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP		(1U << 20)
    69. 

  69. #define SPM_FLAG1_RESERVED_BIT21			(1U << 21)
    70. 

  70. #define SPM_FLAG1_ENABLE_VS1_VOTER			(1U << 22)
    71. 

  71. #define SPM_FLAG1_ENABLE_VS2_VOTER			(1U << 23)
    72. 

  72. #define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL		(1U << 24)
    73. 

  73. #define SPM_FLAG1_RESERVED_BIT25			(1U << 25)
    74. 

  74. #define SPM_FLAG1_RESERVED_BIT26			(1U << 26)
    75. 

  75. #define SPM_FLAG1_RESERVED_BIT27			(1U << 27)
    76. 

  76. #define SPM_FLAG1_RESERVED_BIT28			(1U << 28)
    77. 

  77. #define SPM_FLAG1_RESERVED_BIT29			(1U << 29)
    78. 

  78. #define SPM_FLAG1_RESERVED_BIT30			(1U << 30)
    79. 

  79. #define SPM_FLAG1_DISABLE_CPUEB_OFF			(1U << 31)
    80. 

  80. /* --- SPM DEBUG Define --- */
    81. 

  81. #define SPM_DBG_DEBUG_IDX_26M_WAKE			(1U << 0)
    82. 

  82. #define SPM_DBG_DEBUG_IDX_26M_SLEEP			(1U << 1)
    83. 

  83. #define SPM_DBG_DEBUG_IDX_INFRA_WAKE			(1U << 2)
    84. 

  84. #define SPM_DBG_DEBUG_IDX_INFRA_SLEEP			(1U << 3)
    85. 

  85. #define SPM_DBG_DEBUG_IDX_APSRC_WAKE			(1U << 4)
    86. 

  86. #define SPM_DBG_DEBUG_IDX_APSRC_SLEEP			(1U << 5)
    87. 

  87. #define SPM_DBG_DEBUG_IDX_VRF18_WAKE			(1U << 6)
    88. 

  88. #define SPM_DBG_DEBUG_IDX_VRF18_SLEEP			(1U << 7)
    89. 

  89. #define SPM_DBG_DEBUG_IDX_DDREN_WAKE			(1U << 8)
    90. 

  90. #define SPM_DBG_DEBUG_IDX_DDREN_SLEEP			(1U << 9)
    91. 

  91. #define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC	(1U << 10)
    92. 

  92. #define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE		(1U << 11)
    93. 

  93. #define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE		(1U << 12)
    94. 

  94. #define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN	(1U << 13)
    95. 

  95. #define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE		(1U << 14)
    96. 

  96. #define SPM_DBG_DEBUG_IDX_SYSRAM_SLP			(1U << 15)
    97. 

  97. #define SPM_DBG_DEBUG_IDX_SYSRAM_ON			(1U << 16)
    98. 

  98. #define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP		(1U << 17)
    99. 

  99. #define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON			(1U << 18)
    100. 

  100. #define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP			(1U << 19)
    101. 

  101. #define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON			(1U << 20)
    102. 

  102. #define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP		(1U << 21)
    103. 

  103. #define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON		(1U << 22)
    104. 

  104. #define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V		(1U << 23)
    105. 

  105. #define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V		(1U << 24)
    106. 

  106. #define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V		(1U << 25)
    107. 

  107. #define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V		(1U << 26)
    108. 

  108. #define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW		(1U << 27)
    109. 

  109. #define SPM_DBG_DEBUG_IDX_VTCXO_STATE			(1U << 28)
    110. 

  110. #define SPM_DBG_DEBUG_IDX_INFRA_STATE			(1U << 29)
    111. 

  111. #define SPM_DBG_DEBUG_IDX_VRR18_STATE			(1U << 30)
    112. 

  112. #define SPM_DBG_DEBUG_IDX_APSRC_STATE			(1U << 31)
    113. 

  113. /* --- SPM DEBUG1 Define --- */
    114. 

  114. #define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP		(1U << 0)
    115. 

  115. #define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START		(1U << 1)
    116. 

  116. #define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF			(1U << 2)
    117. 

  117. #define SPM_DBG1_DEBUG_IDX_SYSPLL_ON			(1U << 3)
    118. 

  118. #define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS	(1U << 4)
    119. 

  119. #define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF		(1U << 5)
    120. 

  120. #define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON		(1U << 6)
    121. 

  121. #define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT		(1U << 7)
    122. 

  122. #define SPM_DBG1_RESERVED_BIT8				(1U << 8)
    123. 

  123. #define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF		(1U << 9)
    124. 

  124. #define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON		(1U << 10)
    125. 

  125. #define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC		(1U << 11)
    126. 

  126. #define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M		(1U << 12)
    127. 

  127. #define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K		(1U << 13)
    128. 

  128. #define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M		(1U << 14)
    129. 

  129. #define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF			(1U << 15)
    130. 

  130. #define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON			(1U << 16)
    131. 

  131. #define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW			(1U << 17)
    132. 

  132. #define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH		(1U << 18)
    133. 

  133. #define SPM_DBG1_RESERVED_BIT19				(1U << 19)
    134. 

  134. #define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON	(1U << 20)
    135. 

  135. #define SPM_DBG1_DEBUG_IDX_6315_LOW			(1U << 21)
    136. 

  136. #define SPM_DBG1_DEBUG_IDX_6315_HIGH			(1U << 22)
    137. 

  137. #define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT	(1U << 23)
    138. 

  138. #define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT	(1U << 24)
    139. 

  139. #define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT		(1U << 25)
    140. 

  140. #define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT	(1U << 26)
    141. 

  141. #define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT	(1U << 27)
    142. 

  142. #define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT	(1U << 28)
    143. 

  143. #define SPM_DBG1_RESERVED_BIT29				(1U << 29)
    144. 

  144. #define SPM_DBG1_RESERVED_BIT30				(1U << 30)
    145. 

  145. #define SPM_DBG1_DEBUG_DISABLE_CPUEB_OFF		(1U << 31)
    146. 

  146. 

  147.  /* Macro and Inline */
    148. 

  148. #define is_cpu_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U)
    149. 

  149. #define is_infra_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U)
    150. 

  150. #define is_ddrphy_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U)
    151. 

  151. #endif /* SLEEP_DEF_H */
    152.