cortex_a57.h 3.8 KB

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  1. /*
  2. * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
  3. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-3-Clause
  6. */
  7. #ifndef CORTEX_A57_H
  8. #define CORTEX_A57_H
  9. #include <lib/utils_def.h>
  10. /* Cortex-A57 midr for revision 0 */
  11. #define CORTEX_A57_MIDR U(0x410FD070)
  12. /* Retention timer tick definitions */
  13. #define RETENTION_ENTRY_TICKS_2 U(0x1)
  14. #define RETENTION_ENTRY_TICKS_8 U(0x2)
  15. #define RETENTION_ENTRY_TICKS_32 U(0x3)
  16. #define RETENTION_ENTRY_TICKS_64 U(0x4)
  17. #define RETENTION_ENTRY_TICKS_128 U(0x5)
  18. #define RETENTION_ENTRY_TICKS_256 U(0x6)
  19. #define RETENTION_ENTRY_TICKS_512 U(0x7)
  20. /*******************************************************************************
  21. * CPU Extended Control register specific definitions.
  22. ******************************************************************************/
  23. #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1
  24. #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
  25. #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
  26. #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
  27. #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
  28. #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0)
  29. #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
  30. /*******************************************************************************
  31. * CPU Memory Error Syndrome register specific definitions.
  32. ******************************************************************************/
  33. #define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2
  34. /*******************************************************************************
  35. * CPU Auxiliary Control register specific definitions.
  36. ******************************************************************************/
  37. #define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0
  38. #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)
  39. #define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58)
  40. #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
  41. #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
  42. #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)
  43. #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
  44. #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
  45. #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38)
  46. #define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
  47. #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)
  48. #define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24)
  49. #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25)
  50. #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
  51. /*******************************************************************************
  52. * L2 Control register specific definitions.
  53. ******************************************************************************/
  54. #define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2
  55. #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
  56. #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
  57. #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
  58. #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
  59. #define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21)
  60. /*******************************************************************************
  61. * L2 Extended Control register specific definitions.
  62. ******************************************************************************/
  63. #define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3
  64. #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0)
  65. #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
  66. /*******************************************************************************
  67. * L2 Memory Error Syndrome register specific definitions.
  68. ******************************************************************************/
  69. #define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3
  70. #endif /* CORTEX_A57_H */