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cpus
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aarch64
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cortex_a720.h

cortex_a720.h 1.7 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef CORTEX_A720_H
    8. 

  8. #define CORTEX_A720_H
    9. 

  9. 

  10. #define CORTEX_A720_MIDR					U(0x410FD810)
    11. 

  11. 

  12. /* Cortex A720 loop count for CVE-2022-23960 mitigation */
    13. 

  13. #define CORTEX_A720_BHB_LOOP_COUNT				U(132)
    14. 

  14. 

  15. /*******************************************************************************
    16. 

  16.  * CPU Auxiliary Control register 1 specific definitions.
    17. 

  17.  ******************************************************************************/
    18. 

  18. #define CORTEX_A720_CPUACTLR_EL1				S3_0_C15_C1_0
    19. 

  19. 

  20. /*******************************************************************************
    21. 

  21.  * CPU Auxiliary Control register 2 specific definitions.
    22. 

  22.  ******************************************************************************/
    23. 

  23. #define CORTEX_A720_CPUACTLR2_EL1				S3_0_C15_C1_1
    24. 

  24. 

  25. /*******************************************************************************
    26. 

  26.  * CPU Auxiliary Control register 4 specific definitions.
    27. 

  27.  ******************************************************************************/
    28. 

  28. #define CORTEX_A720_CPUACTLR4_EL1				S3_0_C15_C1_3
    29. 

  29. 

  30. /*******************************************************************************
    31. 

  31.  * CPU Extended Control register specific definitions
    32. 

  32.  ******************************************************************************/
    33. 

  33. #define CORTEX_A720_CPUECTLR_EL1				S3_0_C15_C1_4
    34. 

  34. 

  35. /*******************************************************************************
    36. 

  36.  * CPU Power Control register specific definitions
    37. 

  37.  ******************************************************************************/
    38. 

  38. #define CORTEX_A720_CPUPWRCTLR_EL1				S3_0_C15_C2_7
    39. 

  39. #define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
    40. 

  40. 

  41. #endif /* CORTEX_A720_H */
    42.